Evan Cheng
adeea85f7d
- Switch X86-64 JIT to large code size model.
...
- Re-enable some codegen niceties for X86-64 static relocation model codegen.
- Clean ups, etc.
llvm-svn: 32238
2006-12-05 19:50:18 +00:00
Evan Cheng
456101ebb9
- Use a different wrapper node for RIP-relative GV, etc.
...
- Proper support for both small static and PIC modes under X86-64
- Some (non-optimal) support for medium modes.
llvm-svn: 32046
2006-11-30 21:55:46 +00:00
Evan Cheng
f968824cdb
Custom lower READCYCLECOUNTER for x86-64.
...
llvm-svn: 32017
2006-11-29 08:28:13 +00:00
Chris Lattner
7c265ad682
remove dead/redundant vars
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llvm-svn: 31435
2006-11-03 23:48:56 +00:00
Reid Spencer
db06ed9156
Add debug support for X86/ELF targets (Linux). This allows llvm-gcc4
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generated object modules to be debugged with gdb. Hopefully this helps
pre-release debugging.
llvm-svn: 31299
2006-10-30 22:32:30 +00:00
Evan Cheng
fe5bb5dbe6
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
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llvm-svn: 30945
2006-10-13 21:14:26 +00:00
Chris Lattner
b25677f5ca
Move the Imp tblgen class from the X86 backend to common code.
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llvm-svn: 30907
2006-10-12 17:49:27 +00:00
Chris Lattner
a678c5bac1
Mark ADJCALLSTACKUP/DOWN as clobbering ESP so that virtregmap will notice
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that it can't assume ESP is unmodified across the instrs.
llvm-svn: 30905
2006-10-12 17:42:56 +00:00
Evan Cheng
ca66f49574
Add properties to ComplexPattern.
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llvm-svn: 30891
2006-10-11 21:03:53 +00:00
Evan Cheng
d22f3dd3ed
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
...
llvm-svn: 30844
2006-10-09 20:57:25 +00:00
Evan Cheng
02e193e2ff
Delete dead code; fix 80 col violations.
...
llvm-svn: 30583
2006-09-22 21:43:59 +00:00
Evan Cheng
cfd7b147cf
X86ISD::CMP now produces a chain as well as a flag. Make that the chain
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operand of a conditional branch to allow load folding into CMP / TEST
instructions.
llvm-svn: 30241
2006-09-11 02:19:56 +00:00
Evan Cheng
15dd42884e
Committing X86-64 support.
...
llvm-svn: 30177
2006-09-08 06:48:29 +00:00
Chris Lattner
9c7673ffca
Eliminate X86ISD::TEST, using X86ISD::CMP instead. Match X86ISD::CMP patterns
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using test, which provides nice simplifications like:
- movl %edi, %ecx
- andl $2, %ecx
- cmpl $0, %ecx
+ testl $2, %edi
je LBB1_11 #cond_next90
There are a couple of dagiselemitter deficiencies that this exposes, they will
be handled later.
llvm-svn: 30156
2006-09-07 20:33:45 +00:00
Evan Cheng
798aa508a3
Consistency.
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llvm-svn: 30152
2006-09-07 19:03:48 +00:00
Evan Cheng
34a49551f5
CALLSEQ_* produces chain even if that's not needed.
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llvm-svn: 29603
2006-08-11 09:03:33 +00:00
Evan Cheng
100096b2bb
Clean up.
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llvm-svn: 29228
2006-07-20 21:37:39 +00:00
Evan Cheng
a2eaed93a0
INC / DEC instructions have shorter code size than ADD32ri8, etc.
...
llvm-svn: 29194
2006-07-19 00:27:29 +00:00
Evan Cheng
db529debec
Emit inc / dec of registers as one byte instruction.
...
llvm-svn: 29110
2006-07-11 19:49:49 +00:00
Evan Cheng
1d5fa40da3
Add shift and rotate by 1 instructions / patterns.
...
llvm-svn: 28980
2006-06-29 00:36:51 +00:00
Evan Cheng
a37a2f781e
Remove dead code.
...
llvm-svn: 28938
2006-06-27 20:34:14 +00:00
Evan Cheng
0e2235b803
X86 call instructions can take variable number of operands. Parameters of
...
vector types are passed via XMM registers.
llvm-svn: 28789
2006-06-14 22:24:55 +00:00
Evan Cheng
ed96100b00
Incorrect AT&T opcode.
...
llvm-svn: 28666
2006-06-02 21:09:10 +00:00
Evan Cheng
4488266c46
Rename ASM modifier trunc8, trunc16 to subreg8, subreg16.
...
llvm-svn: 28606
2006-05-31 22:34:26 +00:00
Evan Cheng
f90443c471
Sign extender
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llvm-svn: 28603
2006-05-31 22:05:11 +00:00
Evan Cheng
f7637e403f
A addressing mode folding enhancement:
...
Fold c2 in (x << c1) | c2 where (c2 < c1)
e.g.
int test(int x) {
return (x << 3) + 7;
}
This can be codegen'd as:
leal 7(,%eax,8), %eax
llvm-svn: 28550
2006-05-30 06:59:36 +00:00
Evan Cheng
550e73a900
Remove unused patterns.
...
llvm-svn: 28417
2006-05-20 01:40:16 +00:00
Evan Cheng
3a90665f14
- Use exact-width integer types, e.g. int32_t, to avoid confusion.
...
- Fix a couple of minor bugs in i16immSExt8 and i16immZExt8.
- Added loadiPTR fragment used for indirect jumps and calls.
llvm-svn: 28392
2006-05-19 18:40:54 +00:00
Evan Cheng
ff19d6478e
Explicitly specify MOV32mi can only be used store 32-bit GV, etc.
...
llvm-svn: 28390
2006-05-19 07:30:36 +00:00
Evan Cheng
070813257a
Use generic iPTR instead i32 to represent pointer type.
...
llvm-svn: 28371
2006-05-17 21:21:41 +00:00
Evan Cheng
dc9b5f5fc0
X86 integer register classes naming changes. Make them consistent with FP, vector classes.
...
llvm-svn: 28324
2006-05-16 07:21:53 +00:00
Evan Cheng
0fb3fc3626
Fixing truncate. Previously we were emitting truncate from r16 to r8 as
...
movw. That is we promote the destination operand to r16. So
%CH = TRUNC_R16_R8 %BP
is emitted as
movw %bp, %cx.
This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.
We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.
Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.
llvm-svn: 28164
2006-05-08 08:01:26 +00:00
Evan Cheng
0e9ec8d566
Need extload patterns after Chris' DAG combiner changes
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llvm-svn: 28127
2006-05-05 08:23:07 +00:00
Evan Cheng
84612a59c2
Better implementation of truncate. ISel matches it to a pseudo instruction
...
that gets emitted as movl (for r32 to i16, i8) or a movw (for r16 to i8). And
if the destination gets allocated a subregister of the source operand, then
the instruction will not be emitted at all.
llvm-svn: 28119
2006-05-05 05:40:20 +00:00
Evan Cheng
11e3cec8bd
Make x86 isel lowering produce tailcall nodes. They are match to normal calls
...
for now.
Patch contributed by Alexander Friedman.
llvm-svn: 27994
2006-04-27 08:40:39 +00:00
Nate Begeman
0d74cbcb6b
Optimized stores to the constant pool, while cool, are unnecessary.
...
llvm-svn: 27948
2006-04-22 22:31:45 +00:00
Nate Begeman
7ed816f900
JumpTable support! What this represents is working asm and jit support for
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x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
Evan Cheng
169240beb7
- More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc.
...
- Some bug fixes and naming inconsistency fixes.
llvm-svn: 27377
2006-04-03 20:53:28 +00:00
Evan Cheng
875c895b0f
Added missing (any_extend (load ...)) patterns.
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llvm-svn: 27120
2006-03-25 09:45:48 +00:00
Chris Lattner
ec3f1b5cd1
Fix the encodings of these new instructions, hopefully fixing the JIT
...
failures from last night
llvm-svn: 26981
2006-03-23 16:13:50 +00:00
Nate Begeman
0ec15cd042
Add support for 8 bit immediates with 16/32 bit cmp instructions
...
llvm-svn: 26966
2006-03-23 01:29:48 +00:00
Evan Cheng
8dd794ea70
Use the generic vector register classes VR64 / VR128 rather than V4F32,
...
V8I16, etc.
llvm-svn: 26838
2006-03-18 01:23:20 +00:00
Evan Cheng
ee1a44d5d8
Move some pattern fragments to the right files.
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llvm-svn: 26831
2006-03-17 19:55:52 +00:00
Evan Cheng
d16fa97974
- Nuke 16-bit SBB instructions. We'll never use them.
...
- Nuke a bogus comment.
llvm-svn: 26815
2006-03-17 02:24:04 +00:00
Evan Cheng
d73d06f052
X86ISD::REP_STOS and X86ISD::REP_MOVS now produces a flag.
...
llvm-svn: 26604
2006-03-07 23:34:23 +00:00
Evan Cheng
2327759419
Enable Dwarf debugging info.
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llvm-svn: 26581
2006-03-07 02:02:57 +00:00
Chris Lattner
999aa36a04
remove the read/write port/io intrinsics.
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llvm-svn: 26479
2006-03-03 00:19:58 +00:00
Evan Cheng
995c9806ba
* Allow mul, shl nodes to be codegen'd as LEA (if appropriate).
...
* Add patterns to handle GlobalAddress, ConstantPool, etc.
MOV32ri to materialize these nodes in registers.
ADD32ri to handle %reg + GA, etc.
MOV32mi to handle store GA, etc. to memory.
llvm-svn: 26374
2006-02-25 10:02:21 +00:00
Evan Cheng
cb9fb051a5
- Clean up the lowering and selection code of ConstantPool, GlobalAddress,
...
and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
mentioned leaf nodes. Do not mutate and nodes and do not record the
selection in CodeGenMap. These nodes should be safe to duplicate. This is
a performance win.
llvm-svn: 26335
2006-02-23 20:41:18 +00:00
Evan Cheng
2977507828
PIC related bug fixes.
...
1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.
llvm-svn: 26324
2006-02-23 02:43:52 +00:00