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133 Commits

Author SHA1 Message Date
Evan Cheng
456101ebb9 - Use a different wrapper node for RIP-relative GV, etc. 
- Proper support for both small static and PIC modes under X86-64
- Some (non-optimal) support for medium modes.

llvm-svn: 32046
 2006-11-30 21:55:46 +00:00
Evan Cheng
1e3f41acde Clean up. 
llvm-svn: 32027
 2006-11-29 23:46:27 +00:00
Evan Cheng
7e20347607 Fix for PR1018 - Better support for X86-64 Linux in small code model. 
llvm-svn: 32026
 2006-11-29 23:19:46 +00:00
Evan Cheng
98fa7ab4d7 Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 
of opcode and number of operands.

llvm-svn: 31947
 2006-11-27 23:37:22 +00:00
Evan Cheng
a9176b38f9 For unsigned 8-bit division. Use movzbw to set the lower 8 bits of AX while 
clearing the upper 8-bits instead of issuing two instructions. This also
eliminates the need to target the AH register which can be problematic on
x86-64.

llvm-svn: 31832
 2006-11-17 22:10:14 +00:00
Bill Wendling
b6061e32fa Removed even more std::cerr and #include <iostream> things. 
llvm-svn: 31813
 2006-11-17 07:52:03 +00:00
Evan Cheng
0e82270ff2 Matches MachineInstr changes. 
llvm-svn: 31712
 2006-11-13 23:36:35 +00:00
Evan Cheng
b9e2ae9e37 Add implicit use / def operands to created MI's. 
llvm-svn: 31676
 2006-11-11 10:21:44 +00:00
Evan Cheng
f880ed86ff Add all implicit defs to FP_REG_KILL mi. 
llvm-svn: 31674
 2006-11-11 07:19:36 +00:00
Evan Cheng
3a017e8abd Fix a bug in SelectScalarSSELoad. Since the load is wrapped in a 
SCALAR_TO_VECTOR, even if the hasOneUse() check pass we may end up folding
the load into two instructions. Make sure we check the SCALAR_TO_VECTOR
has only one use as well.

llvm-svn: 31641
 2006-11-10 21:23:04 +00:00
Evan Cheng
736a8eb3cd Match tblegen changes. 
llvm-svn: 31571
 2006-11-08 20:34:28 +00:00
Jeff Cohen
e1003da1a2 Unbreak VC++ build. 
llvm-svn: 31464
 2006-11-05 19:31:28 +00:00
Chris Lattner
24e8fdc1f6 silence warning 
llvm-svn: 31393
 2006-11-03 01:13:15 +00:00
Evan Cheng
c73547a71d SelectScalarSSELoad should call CanBeFoldedBy as well. 
llvm-svn: 30973
 2006-10-16 06:34:55 +00:00
Evan Cheng
6c8de88f88 Corrected load folding check. We need to start from the root of the sub-dag 
being matched and ensure there isn't a non-direct path to the load (i.e. a
path that goes out of the sub-dag.)

llvm-svn: 30958
 2006-10-14 08:33:25 +00:00
Evan Cheng
fe5bb5dbe6 Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. 
llvm-svn: 30945
 2006-10-13 21:14:26 +00:00
Evan Cheng
76d365ac84 Doh. This wasn't causing problems by luck. 
llvm-svn: 30914
 2006-10-12 19:13:59 +00:00
Chris Lattner
fde6859201 fix compilation failure of smg2000 
llvm-svn: 30900
 2006-10-12 03:55:48 +00:00
Chris Lattner
502246c4a6 Fold "zero extending vector loads" now that evan added the chain manip stuff. 
This compiles both tests in X86/vec_ss_load_fold.ll into:

_test1:
        movss 4(%esp), %xmm0
        subss LCPI1_0, %xmm0
        mulss LCPI1_1, %xmm0
        minss LCPI1_2, %xmm0
        xorps %xmm1, %xmm1
        maxss %xmm1, %xmm0
        cvttss2si %xmm0, %eax
        andl $65535, %eax
        ret

instead of:

_test1:
        movss LCPI1_0, %xmm0
        movss 4(%esp), %xmm1
        subss %xmm0, %xmm1
        movss LCPI1_1, %xmm0
        mulss %xmm0, %xmm1
        movss LCPI1_2, %xmm0
        minss %xmm0, %xmm1
        xorps %xmm0, %xmm0
        maxss %xmm0, %xmm1
        cvttss2si %xmm1, %eax
        andl $65535, %eax
        ret

llvm-svn: 30894
 2006-10-11 22:09:58 +00:00
Evan Cheng
95140c9c64 ComplexPatterns sse_load_f32 and sse_load_f64 returns in / out chain operands. 
llvm-svn: 30892
 2006-10-11 21:06:01 +00:00
Evan Cheng
b2998e15f2 More isel time load folding checking for nodes that produce flag values. 
See comment in CanBeFoldedBy() for detailed explanation.

llvm-svn: 30851
 2006-10-10 01:46:56 +00:00
Evan Cheng
d22f3dd3ed Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. 
llvm-svn: 30844
 2006-10-09 20:57:25 +00:00
Chris Lattner
3cd1d08ac6 completely disable folding of loads into scalar sse instructions and provide 
a framework for doing it right.  This fixes
CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll.

Once X86DAGToDAGISel::SelectScalarSSELoad is implemented right, this task
will be done.

llvm-svn: 30817
 2006-10-07 21:55:32 +00:00
Evan Cheng
82dcacb63d Not needed. 
llvm-svn: 30674
 2006-09-29 22:05:10 +00:00
Anton Korobeynikov
7c2118575c Added some eye-candy for Subtarget type checking 
Added X86 StdCall & FastCall calling conventions. Codegen will follow.

llvm-svn: 30446
 2006-09-17 20:25:45 +00:00
Evan Cheng
e9bbf85e5e Remove a unnecessary check. 
llvm-svn: 30382
 2006-09-14 23:55:02 +00:00
Chris Lattner
89d7fe3917 Fix a regression in the 32-bit port from the 64-bit port landing. 
We now compile CodeGen/X86/lea-2.ll into:

_test:
        movl 4(%esp), %eax
        movl 8(%esp), %ecx
        leal -5(%ecx,%eax,4), %eax
        ret

instead of:

_test:
        movl 4(%esp), %eax
        leal (,%eax,4), %eax
        addl 8(%esp), %eax
        addl $4294967291, %eax
        ret

llvm-svn: 30288
 2006-09-13 04:45:25 +00:00
Evan Cheng
dd52a60189 Reflects MachineConstantPoolEntry changes. 
llvm-svn: 30279
 2006-09-12 21:04:05 +00:00
Evan Cheng
15dd42884e Committing X86-64 support. 
llvm-svn: 30177
 2006-09-08 06:48:29 +00:00
Evan Cheng
69ef4ae2a1 Oops. Bad typo. Without the check of N1.hasOneUse() bad things can happen. 
Suppose the TokenFactor can reach the Op:

       [Load chain]
           ^
           |
         [Load]
         ^    ^
         |    |
        /      \-
       /         |
      /          [Op]
     /          ^ ^
     |        ..  |
     |       /    |
   [TokenFactor]  |
       ^          |
       |          |
        \        /
         \      /
         [Store]

If we move the Load below the TokenFactor, we would have created a cycle in
the DAG.

llvm-svn: 30040
 2006-09-01 22:52:28 +00:00
Evan Cheng
9fda1129ce Remove dead code. 
llvm-svn: 29962
 2006-08-29 21:42:58 +00:00
Evan Cheng
b747dc2ab0 Don't performance load/op/store transformation if op produces a floating point 
or vector result. X86 does not have load/mod/store variants of those
instructions.

llvm-svn: 29957
 2006-08-29 18:37:37 +00:00
Evan Cheng
4c63a7ed05 - Enable x86 isel preprocessing by default unless -fast is specified. 
- Also disable isel load folding if -fast.

llvm-svn: 29956
 2006-08-29 18:28:33 +00:00
Evan Cheng
3f6a206f01 Avoid making unneeded load/mod/store transformation which can hurt performance. 
llvm-svn: 29952
 2006-08-29 06:44:17 +00:00
Evan Cheng
25d25dd384 Add an optional pass to preprocess the DAG before x86 isel to allow selecting more load/mod/store instructions. 
llvm-svn: 29943
 2006-08-28 20:10:17 +00:00
Chris Lattner
33bd5dcfb7 s|llvm/Support/Visibility.h|llvm/Support/Compiler.h| 
llvm-svn: 29911
 2006-08-27 12:54:02 +00:00
Evan Cheng
a6f81f1863 Do not use getTargetNode() and SelectNodeTo() which takes more than 3 
SDOperand arguments. Use the variants which take an array and number instead.

llvm-svn: 29907
 2006-08-27 08:14:06 +00:00
Evan Cheng
1c3d571e4b SelectNodeTo now returns a SDNode*. 
llvm-svn: 29901
 2006-08-26 08:00:10 +00:00
Evan Cheng
2db7799507 Select() no longer require Result operand by reference. 
llvm-svn: 29898
 2006-08-26 05:34:46 +00:00
Evan Cheng
57893e39fe Match tblgen changes; clean up. 
llvm-svn: 29894
 2006-08-26 01:05:16 +00:00
Evan Cheng
33c5017ffb Doh. Incorrectly inverted condition. Also add a isOnlyUse check to match tablegen. 
llvm-svn: 29741
 2006-08-16 23:59:00 +00:00
Evan Cheng
7fb75bbc8d SelectNodeTo() may return a SDOperand that is different from the input. 
llvm-svn: 29726
 2006-08-16 07:30:09 +00:00
Evan Cheng
6053206580 Match tablegen changes. 
llvm-svn: 29604
 2006-08-11 09:08:15 +00:00
Evan Cheng
01cd84d113 Eliminate reachability matrix. It has to be calculated before any instruction 
selection is done. That's rather expensive especially in situations where it
isn't really needed.
Move back to a searching the predecessors, but make use of topological order
to trim the search space.

llvm-svn: 29559
 2006-08-08 00:31:00 +00:00
Evan Cheng
d18be1d9c1 Match tablegen isel changes. 
llvm-svn: 29549
 2006-08-07 22:28:20 +00:00
Evan Cheng
445674348f Reflect change to AssignTopologicalOrder(). 
llvm-svn: 29480
 2006-08-02 22:01:32 +00:00
Evan Cheng
6fd2b20b8a Use of vector<bool> causes some horrendous compile time regression (2x)! 
Looks like libstdc++ implementation does not scale very well. Switch back
to using directly managed arrays.

llvm-svn: 29469
 2006-08-02 09:18:33 +00:00
Evan Cheng
29d6f9d252 Factor topological order code to SelectionDAG. Clean up. 
llvm-svn: 29430
 2006-08-01 08:17:22 +00:00
Evan Cheng
e4c19806cd Can't spell. 
llvm-svn: 29383
 2006-07-28 06:33:41 +00:00
Evan Cheng
8ea5ac0abd Some clean up. 
llvm-svn: 29382
 2006-07-28 06:05:06 +00:00