Bill Wendling
f13d78d3b8
What should be the last unnecessary <iostream>s in the library.
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llvm-svn: 32333
2006-12-07 22:21:48 +00:00
Evan Cheng
98fa7ab4d7
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
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of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
Rafael Espindola
5daebfdae0
implement load effective address similar to the alpha backend
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remove lea_addri and the now unused memri addressing mode
llvm-svn: 31592
2006-11-09 13:58:55 +00:00
Rafael Espindola
f7b898d497
initial implementation of addressing mode 2
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TODO: fix lea_addri
llvm-svn: 31552
2006-11-08 17:07:32 +00:00
Rafael Espindola
ba8771a3db
add support for calling functions when the caller has variable sized objects
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llvm-svn: 31312
2006-10-31 13:03:26 +00:00
Rafael Espindola
99322ef58c
initial support for frame pointers
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llvm-svn: 31197
2006-10-26 13:31:26 +00:00
Rafael Espindola
d5a6eaec14
add the immediate to the Offset in eliminateFrameIndex
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llvm-svn: 30998
2006-10-17 14:34:02 +00:00
Rafael Espindola
01400015fc
add FCPYS and FCPYD
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llvm-svn: 30995
2006-10-17 13:13:23 +00:00
Rafael Espindola
f35563ff66
fix the stack alignment
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llvm-svn: 30766
2006-10-06 14:29:47 +00:00
Rafael Espindola
1a3020bfcf
add shifts to addressing mode 1
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llvm-svn: 30291
2006-09-13 12:09:43 +00:00
Rafael Espindola
89ac048c5d
partial implementation of the ARM Addressing Mode 1
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llvm-svn: 30252
2006-09-11 17:25:40 +00:00
Chris Lattner
9cd4e3429e
Completely eliminate def&use operands. Now a register operand is EITHER a
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def operand or a use operand.
llvm-svn: 30109
2006-09-05 02:31:13 +00:00
Rafael Espindola
ff879761c1
add a "load effective address"
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llvm-svn: 29748
2006-08-17 17:09:40 +00:00
Rafael Espindola
b98e92cb78
Declare the callee saved regs
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Remove the hard coded store and load of the link register
Implement ARMFrameInfo
llvm-svn: 29727
2006-08-16 14:43:33 +00:00
Rafael Espindola
2ddcf46717
correctly set LocalAreaOffset of TargetFrameInfo
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llvm-svn: 29589
2006-08-09 17:37:45 +00:00
Rafael Espindola
f0b265b48b
fix the spill code
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llvm-svn: 29583
2006-08-09 16:41:12 +00:00
Rafael Espindola
9e8af5c486
fix the loading of the link register in emitepilogue
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llvm-svn: 29580
2006-08-09 13:15:47 +00:00
Rafael Espindola
ae2d1c53c7
change the addressing mode of the str instruction to reg+imm
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llvm-svn: 29571
2006-08-08 20:35:03 +00:00
Rafael Espindola
7bfbb91f75
initial support for variable number of arguments
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llvm-svn: 29567
2006-08-08 13:02:29 +00:00
Rafael Espindola
9ea0bc742c
implemented sub
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correctly update the stack pointer in the prologue and epilogue
llvm-svn: 29244
2006-07-21 12:26:16 +00:00
Rafael Espindola
ad256854c0
initial prologue and epilogue implementation. Need to define add and sub before finishing it :-)
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llvm-svn: 29175
2006-07-18 17:00:30 +00:00
Rafael Espindola
fdfaee67f5
add the memri memory operand
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this makes it possible for ldr instructions with non-zero immediate
llvm-svn: 29103
2006-07-11 11:36:48 +00:00
Rafael Espindola
071c83dff0
create the raddr addressing mode that matches any register and the frame index
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use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
llvm-svn: 29079
2006-07-10 01:41:35 +00:00
Rafael Espindola
f11f34a3d6
handle the "mov reg1, reg2" case in isMoveInstr
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llvm-svn: 28945
2006-06-27 21:52:45 +00:00
Rafael Espindola
14a59f5b6e
initial implementation of ARMRegisterInfo::eliminateFrameIndex
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fixes test/Regression/CodeGen/ARM/ret_arg5.ll
llvm-svn: 28854
2006-06-18 00:08:07 +00:00
Rafael Espindola
a0e82ff9be
implement movri
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add a stub LowerFORMAL_ARGUMENTS
llvm-svn: 28388
2006-05-18 21:45:49 +00:00
Evan Cheng
667b133ab9
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
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llvm-svn: 28378
2006-05-18 00:12:58 +00:00
Rafael Espindola
dd49dfc0df
added a skeleton of the ARM backend
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llvm-svn: 28301
2006-05-14 22:18:28 +00:00
