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182 Commits

Author SHA1 Message Date
Evan Cheng
e2e899b5c2 Don't forget about sub-register indices when rematting instructions. 
llvm-svn: 49830
 2008-04-16 23:44:44 +00:00
Nicolas Geoffray
82baa2d2c6 Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented 
llvm-svn: 49809
 2008-04-16 20:10:13 +00:00
Dan Gohman
d7301ea935 Rename MemOperand to MachineMemOperand. This was suggested by 
review feedback from Chris quite a while ago. No functionality
change.

llvm-svn: 49348
 2008-04-07 19:35:22 +00:00
Evan Cheng
e1eee9570f ReMat of load from stub in pic mode extends the life of pic base. Currently spiller doesn't do a good job of estimating the impact. Disable for now. 
llvm-svn: 49059
 2008-04-01 23:26:12 +00:00
Evan Cheng
5c98bdbc4f Remove unnecessary and non-deterministic checking code. Re-enable remat of load from gv stub. 
llvm-svn: 49054
 2008-04-01 21:38:20 +00:00
Evan Cheng
d7f2ac9a0a Disabling remat of load from gv stub (temporarily) again to fix llvmgcc bootstrap miscompare. 
llvm-svn: 49037
 2008-04-01 07:33:13 +00:00
Evan Cheng
a3ce7b4c76 It's not safe to fold a load from GV stub or constantpool into a two-address use. 
llvm-svn: 49002
 2008-03-31 23:19:51 +00:00
Evan Cheng
38a755499d Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. 
llvm-svn: 48995
 2008-03-31 20:40:39 +00:00
Evan Cheng
38bfff8a16 Re-apply 48911. 
llvm-svn: 48977
 2008-03-31 07:54:19 +00:00
Evan Cheng
10d0aba260 Backing out 48911 for now. It's breaking stuff. 
llvm-svn: 48922
 2008-03-28 17:49:06 +00:00
Evan Cheng
d66e48366f Load from stub is already re-materializable. 
llvm-svn: 48911
 2008-03-28 06:49:25 +00:00
Evan Cheng
e66720fd57 Code clean up. 
llvm-svn: 48856
 2008-03-27 01:45:11 +00:00
Evan Cheng
aca67f0b29 Allow certain lea instructions to be rematerialized. 
llvm-svn: 48855
 2008-03-27 01:41:09 +00:00
Evan Cheng
1afaf3092f Remove an unused command line option. 
llvm-svn: 48854
 2008-03-27 01:30:24 +00:00
Dan Gohman
58ad056286 Add CMP32mr and friends to the load-unfolding table. Among 
other things, this allows the scheduler to unfold a load operand
in the 2008-01-08-SchedulerCrash.ll testcase, so it now successfully
clones the comparison to avoid a pushf+popf.

llvm-svn: 48777
 2008-03-25 16:53:19 +00:00
Chris Lattner
8a4fa95cae Add support for calls that return two FP values in 
ST(0)/ST(1).

llvm-svn: 48634
 2008-03-21 06:38:26 +00:00
Christopher Lamb
b4f4b41048 Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. 
llvm-svn: 48412
 2008-03-16 03:12:01 +00:00
Christopher Lamb
0f1c32eb63 Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. 
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329
 2008-03-13 05:47:01 +00:00
Chris Lattner
4458eecb7a coalesce away 80-bit floating point copies. 
llvm-svn: 48241
 2008-03-11 19:30:09 +00:00
Chris Lattner
aa2287714e convert a massive if statement to a switch. 
llvm-svn: 48240
 2008-03-11 19:28:17 +00:00
Christopher Lamb
4d5034cf91 Missed part of recommit. 
llvm-svn: 48224
 2008-03-11 10:27:36 +00:00
Chris Lattner
d1a014af4e abort with an assert instead of a cerr to get line# 
llvm-svn: 48199
 2008-03-10 23:56:08 +00:00
Evan Cheng
067ecbc341 Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests. 
llvm-svn: 48167
 2008-03-10 19:31:26 +00:00
Christopher Lamb
32e5ce3d96 Allow insert_subreg into implicit, target-specific values. 
Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.

llvm-svn: 48130
 2008-03-10 06:12:08 +00:00
Chris Lattner
b6bfedbcfd teach X86InstrInfo::copyRegToReg how to copy into ST(0) from 
an RFP register class.

Teach ScheduleDAG how to handle CopyToReg with different src/dst 
reg classes.

This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.

llvm-svn: 48107
 2008-03-09 09:15:31 +00:00
Chris Lattner
b29a963cf5 add some code to support cross-register class copying from 
RST -> RFP{32/64/80}.  We only handle ST(0) for now.

llvm-svn: 48104
 2008-03-09 08:46:19 +00:00
Chris Lattner
53b86390b7 rearrange some code, no functionality change. 
llvm-svn: 48101
 2008-03-09 07:58:04 +00:00
Evan Cheng
d3e9e78aa0 Turning on remat of pic loads. 
llvm-svn: 47524
 2008-02-23 02:07:42 +00:00
Evan Cheng
97ca29e99a No need recognize load from a fixed argument slot as re-materializable. LiveIntervalAnalysis already handles it as a special case. 
llvm-svn: 47522
 2008-02-23 01:47:44 +00:00
Evan Cheng
1b417c4d84 Allow re-materialization of pic load (controlled by -remat-pic-load for now). 
llvm-svn: 47476
 2008-02-22 09:25:47 +00:00
Evan Cheng
4b37f5ff05 commuteInstr() can now commute non-ssa machine instrs. 
llvm-svn: 47043
 2008-02-13 02:46:49 +00:00
Evan Cheng
90f03a0b88 It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. 
llvm-svn: 46893
 2008-02-08 21:20:40 +00:00
Evan Cheng
b2bc19ee5b Added missing entries in X86 load / store folding tables. 
llvm-svn: 46866
 2008-02-08 00:12:56 +00:00
Evan Cheng
92635b3d94 In some cases, e.g. ADD32ri, no transformation is made. Guide against it. 
llvm-svn: 46849
 2008-02-07 08:29:53 +00:00
Chris Lattner
5e112f44c8 fix a wordo that gordon noticed :) 
llvm-svn: 45896
 2008-01-12 00:53:16 +00:00
Chris Lattner
0242c393d1 Any x86 instruction that reads from an invariant location is invariant. 
This allows us to sink things like:
	cvtsi2sd	32(%esp), %xmm1
when reading from the argument area, for example.

llvm-svn: 45895
 2008-01-12 00:35:08 +00:00
Chris Lattner
0293fca6d8 rename MachineInstr::setInstrDescriptor -> setDesc 
llvm-svn: 45871
 2008-01-11 18:10:50 +00:00
Chris Lattner
a83f66d1bb remove xchg and shift-reg-by-1 instructions, which are dead. 
llvm-svn: 45870
 2008-01-11 18:00:50 +00:00
Chris Lattner
bfffa4f21e Simplify the side effect stuff a bit more and make licm/sinking 
both work right according to the new flags.

This removes the TII::isReallySideEffectFree predicate, and adds
TII::isInvariantLoad. 

It removes NeverHasSideEffects+MayHaveSideEffects and adds
UnmodeledSideEffects as machine instr flags.  Now the clients
can decide everything they need.

I think isRematerializable can be implemented in terms of the
flags we have now, though I will let others tackle that.

llvm-svn: 45843
 2008-01-10 23:08:24 +00:00
Chris Lattner
8e486a6b25 verify that the frame index is immutable before remat'ing (still disabled) 
or being side-effect free.

llvm-svn: 45816
 2008-01-10 04:16:31 +00:00
Chris Lattner
c465555fe6 add a testcase 
llvm-svn: 45768
 2008-01-09 00:37:18 +00:00
Bill Wendling
b94c1f2999 Operand 1 should be a register. We don't care if it's a preg, vreg, or 0. 
llvm-svn: 45699
 2008-01-07 08:05:29 +00:00
Chris Lattner
f83aae613c rename TargetInstrDescriptor -> TargetInstrDesc. 
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695
 2008-01-07 07:27:27 +00:00
Chris Lattner
9d38dfa4a5 Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor 
llvm-svn: 45680
 2008-01-07 03:13:06 +00:00
Chris Lattner
55343065e3 remove MachineOpCode typedef. 
llvm-svn: 45679
 2008-01-07 02:48:55 +00:00
Chris Lattner
93e1e6ee12 Add predicates methods to TargetOperandInfo, and switch all clients 
over to using them, instead of diddling Flags directly.  Change the
various flags from const variables to enums.

llvm-svn: 45677
 2008-01-07 02:39:19 +00:00
Chris Lattner
f7f96d818f Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects 
that it is cheap and efficient to get.

Move a variety of predicates from TargetInstrInfo into 
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around.  Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.

Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.

llvm-svn: 45674
 2008-01-07 01:56:04 +00:00
Owen Anderson
f19692b2f6 Move even more functionality from MRegisterInfo into TargetInstrInfo. 
Some day I'll get it all moved over...

llvm-svn: 45672
 2008-01-07 01:35:02 +00:00
Bill Wendling
703a1fc174 Fix comment. 
llvm-svn: 45638
 2008-01-05 23:30:51 +00:00
Bill Wendling
ecf0f85985 Chris and Evan noticed that this check was compleatly fubared. I was 
checking that there was a from a global instead of a load from the stub
for a global, which is the one that's safe to hoist.

Consider this program:

volatile char G[100];
int B(char *F, int N) {
  for (; N > 0; --N)
    F[N] = G[N];
}

In static mode, we shouldn't be hoisting the load from G:

$ llc -relocation-model=static -o - a.bc -march=x86 -machine-licm

LBB1_1: # bb.preheader
        leal    -1(%eax), %edx
        testl   %edx, %edx
        movl    $1, %edx
        cmovns  %eax, %edx
        xorl    %esi, %esi
LBB1_2: # bb
        movb    _G(%eax), %bl
        movb    %bl, (%ecx,%eax)

llvm-svn: 45626
 2008-01-05 09:18:04 +00:00