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3552 Commits

Author SHA1 Message Date
Jakub Staszak
2873980483 Fix #include guard directive. 
llvm-svn: 135947
 2011-07-25 20:08:00 +00:00
Jakub Staszak
5c309cbead Rename BlockFrequency to BlockFrequencyInfo and MachineBlockFrequency to 
MachineBlockFrequencyInfo.

llvm-svn: 135937
 2011-07-25 19:25:40 +00:00
Bill Wendling
a289f709aa Add a method to set the compact unwind info. 
llvm-svn: 135806
 2011-07-22 21:17:05 +00:00
Jakub Staszak
cf5ebedf56 Allow getBlockFreq to return 0. 
llvm-svn: 135742
 2011-07-22 02:24:57 +00:00
Evan Cheng
c9bc5a9011 Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc. 
There is still a bit more refactoring left to do in Targets. But we are now very
close to fixing all the layering issues in MC.

llvm-svn: 135611
 2011-07-20 19:50:42 +00:00
Evan Cheng
380dc98371 Add MCObjectFileInfo and sink the MCSections initialization code from 
TargetLoweringObjectFileImpl down to MCObjectFileInfo.

TargetAsmInfo is done to one last method. It's *almost* gone!

llvm-svn: 135569
 2011-07-20 05:58:47 +00:00
Devang Patel
72886ba8d8 Revert r135423. 
llvm-svn: 135454
 2011-07-19 00:28:24 +00:00
Bill Wendling
b1d5a0798a Rename CompactEncoding to CompactUnwindEncoding. 
llvm-svn: 135448
 2011-07-19 00:00:58 +00:00
Bill Wendling
203796ee7a Move the compact encoding from the target-specific library to the code-gen 
library.

llvm-svn: 135443
 2011-07-18 23:38:40 +00:00
Evan Cheng
10c6820ff4 Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for 
better location welcome).

llvm-svn: 135438
 2011-07-18 22:29:13 +00:00
Evan Cheng
561d71ce7b Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down 
to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.

llvm-svn: 135424
 2011-07-18 20:57:22 +00:00
Devang Patel
389cb9d8c6 During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases. 
[take 2]

llvm-svn: 135423
 2011-07-18 20:55:23 +00:00
Chris Lattner
e1fe7061ce land David Blaikie's patch to de-constify Type, with a few tweaks. 
llvm-svn: 135375
 2011-07-18 04:54:35 +00:00
Jakub Staszak
a0010953f7 Add MachineBlockFrequency analysis. 
llvm-svn: 135352
 2011-07-16 20:23:20 +00:00
Jakob Stoklund Olesen
987cd08002 Extract parts of RAGreedy::splitAroundRegion as SplitKit methods. 
This gets rid of some of the gory splitting details in RAGreedy and
makes them available to future SplitKit clients.

Slightly generalize the functionality to support multi-way splitting.
Specifically, SplitEditor::splitLiveThroughBlock() supports switching
between different register intervals in a block.

llvm-svn: 135307
 2011-07-15 21:47:57 +00:00
Evan Cheng
7bdc771798 Fix up TargetLoweringObjectFile ctors to properly initialize fields. 
llvm-svn: 135068
 2011-07-13 19:54:59 +00:00
Jay Foad
88fb4f4597 Convert InsertValueInst and ExtractValueInst APIs to use ArrayRef. 
llvm-svn: 135040
 2011-07-13 10:26:04 +00:00
Jakub Staszak
a8987cb392 - Make BranchProbability constructor public. 
- Add getCompl() method.

llvm-svn: 134857
 2011-07-10 02:12:39 +00:00
Cameron Zwarich
c23366d357 Add an intrinsic and codegen support for fused multiply-accumulate. The intent 
is to use this for architectures that have a native FMA instruction.

llvm-svn: 134742
 2011-07-08 21:39:21 +00:00
Jakob Stoklund Olesen
acaf9e9ce1 Be more aggressive about following hints. 
RAGreedy::tryAssign will now evict interference from the preferred
register even when another register is free.

To support this, add the EvictionCost struct that counts how many hints
are broken by an eviction. We don't want to break one hint just to
satisfy another.

Rename canEvict to shouldEvict, and add the first bit of eviction policy
that doesn't depend on spill weights: Always make room in the preferred
register as long as the evictees can be split and aren't already
assigned to their preferred register.

Also make the CSR avoidance more accurate. When looking for a cheaper
register it is OK to use a new volatile register. Only CSR aliases that
have never been used before should be avoided.

llvm-svn: 134735
 2011-07-08 20:46:18 +00:00
Lang Hames
9e52663aa4 Add functions 'hasPredecessor' and 'hasPredecessorHelper' to SDNode. The 
hasPredecessorHelper function allows predecessors to be cached to speed up
repeated invocations. This fixes PR10186.

X.isPredecessorOf(Y) now just calls Y.hasPredecessor(X)

Y.hasPredecessor(X) calls Y.hasPredecessorHelper(X, Visited, Worklist) with
empty Visited and Worklist sets (i.e. no caching over invocations).

Y.hasPredecessorHelper(X, Visited, Worklist) caches search state in Visited
and Worklist to speed up repeated calls. The Visited set is searched for X
before going to the worklist to further search the DAG if necessary.

llvm-svn: 134592
 2011-07-07 04:31:51 +00:00
Jakob Stoklund Olesen
c19c47697f Include a source location when complaining about bad inline assembly. 
Add a MI->emitError() method that the backend can use to report errors
related to inline assembly. Call it from X86FloatingPoint.cpp when the
constraints are wrong.

This enables proper clang diagnostics from the backend:

$ clang -c pr30848.c
pr30848.c:5:12: error: Inline asm output regs must be last on the x87 stack
  __asm__ ("" : "=u" (d));  /* { dg-error "output regs" } */
           ^
1 error generated.

llvm-svn: 134307
 2011-07-02 03:53:34 +00:00
Rafael Espindola
83789b3b8d Create a isFullCopy predicate. 
llvm-svn: 134189
 2011-06-30 21:15:52 +00:00
Devang Patel
66c4bc1dda Revert r133953 for now. 
llvm-svn: 134116
 2011-06-29 23:50:13 +00:00
Evan Cheng
4a169be530 - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and 
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
 2011-06-28 19:10:37 +00:00
Evan Cheng
f79231cbd4 Remove RegClass2VRegMap from MachineRegisterInfo. 
llvm-svn: 133967
 2011-06-27 23:54:40 +00:00
Evan Cheng
7df851a4ff Remove the experimental (and unused) pre-ra splitting pass. Greedy regalloc can split live ranges. 
llvm-svn: 133962
 2011-06-27 23:40:45 +00:00
Devang Patel
8fbd4b55ea During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases. 
llvm-svn: 133953
 2011-06-27 22:32:04 +00:00
Rafael Espindola
45a2fa5664 There is only one register coalescer. Merge it into the base class and 
remove the analysis group.

llvm-svn: 133899
 2011-06-26 22:34:10 +00:00
Rafael Espindola
7ad658a832 Move RegisterCoalescer.h to lib/CodeGen. 
llvm-svn: 133895
 2011-06-26 21:41:06 +00:00
Devang Patel
91fee59b74 Handle debug info for i128 constants. 
llvm-svn: 133821
 2011-06-24 20:46:11 +00:00
Jay Foad
9dc6571cbc Fix a FIXME by making GlobalVariable::getInitializer() return a 
const Constant *.

llvm-svn: 133400
 2011-06-19 18:37:11 +00:00
Benjamin Kramer
0b4d4ce7c1 Don't allocate empty read-only SmallVectors during SelectionDAG deallocation. 
llvm-svn: 133348
 2011-06-18 13:13:44 +00:00
Eric Christopher
25aa04466a Lower multiply with overflow checking to __mulo<mode> 
calls if we haven't been able to lower them any
other way.

Fixes rdar://9090077 and rdar://9210061

llvm-svn: 133288
 2011-06-17 20:41:29 +00:00
Lang Hames
20552cda1a Add a hook for PBQP clients to run a custom pre-alloc pass to run prior to PBQP allocation. Patch by Arnaud Allard de Grandmaison. 
llvm-svn: 133249
 2011-06-17 07:09:01 +00:00
Jakub Staszak
5c7b7d64ba Introduce MachineBranchProbabilityInfo class, which has similar API to 
BranchProbabilityInfo (expect setEdgeWeight which is not available here).
Branch Weights are kept in MachineBasicBlocks. To turn off this analysis
set -use-mbpi=false.

llvm-svn: 133184
 2011-06-16 20:22:37 +00:00
Owen Anderson
a9bf21548f Fix formatting. 
llvm-svn: 133164
 2011-06-16 16:52:24 +00:00
Owen Anderson
f98c2ea49d Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match. 
llvm-svn: 133106
 2011-06-15 23:35:18 +00:00
Andrew Trick
ce93f28a36 Added -stress-sched flag in the Asserts build. 
Added a test case for handling physreg aliases during pre-RA-sched.

llvm-svn: 133063
 2011-06-15 17:16:12 +00:00
Bruno Cardoso Lopes
b6afc5168f Add one more argument to the prefetch intrinsic to indicate whether it's a data 
or instruction cache access. Update the targets to match it and also teach
autoupgrade.

llvm-svn: 132976
 2011-06-14 04:58:37 +00:00
Bill Wendling
0f5a6fb66c Reformatting. Moving class definitions to more natural places. No functionalogical changes. 
llvm-svn: 132876
 2011-06-11 11:37:49 +00:00
Cameron Zwarich
a54eaeb7ae Provide an ARMCCState subclass of CCState so that ARM clients will always set 
CallOrPrologue correctly and eliminate the existing setter.

llvm-svn: 132856
 2011-06-10 20:59:24 +00:00
Cameron Zwarich
7f353f2163 Rename the ParmContext enum values to make a bit more sense and add a small 
comment on their meaning.

llvm-svn: 132854
 2011-06-10 20:37:36 +00:00
Cameron Zwarich
cc21e3fc58 Remove tabs. 
llvm-svn: 132853
 2011-06-10 20:31:39 +00:00
Eric Christopher
1ae9ec6124 Add a parameter to CCState so that it can access the MachineFunction. 
No functional change.

Part of PR6965

llvm-svn: 132763
 2011-06-08 23:55:35 +00:00
Lang Hames
642b95ac13 Switched to DenseMap for allowed sets in PBQP. Reduces total LLC time by 15% on CINT2006 for x86-32. 
llvm-svn: 132707
 2011-06-07 06:05:58 +00:00
Devang Patel
7b9fc618b2 Remove dead code. 
llvm-svn: 132488
 2011-06-02 21:31:00 +00:00
Chad Rosier
945a780b4e Typos. 
llvm-svn: 132437
 2011-06-01 23:32:40 +00:00
Charles Davis
6702c786ed When generating code for Win64 EH, emit StartProc and EndProc directives. 
llvm-svn: 132250
 2011-05-28 04:21:04 +00:00
Rafael Espindola
2230168a0f Make size computation less brittle. 
llvm-svn: 132222
 2011-05-27 22:05:41 +00:00