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24 Commits

Author SHA1 Message Date
Craig Topper
f8c17bbd8f [X86] Add some missing reversed forms of XOP instructions. 
llvm-svn: 261417
 2016-02-20 06:20:17 +00:00
Simon Pilgrim
ac4c196247 [X86][XOP] Add support for the matching of the VPCMOV bit select instruction 
XOP has the VPCMOV instruction that performs the common vector bit select operation OR( AND( SRC1, SRC3 ), AND( SRC2, ~SRC3 ) )

This patch adds tablegen pattern matching for this instruction.

Differential Revision: http://reviews.llvm.org/D8841

llvm-svn: 251975
 2015-11-03 20:27:01 +00:00
Simon Pilgrim
a6b49e0950 [X86][XOP] Add VPROT instruction opcodes 
Added X86ISD opcodes for VPROT vector rotate by variable and by immediate.

llvm-svn: 250620
 2015-10-17 19:04:24 +00:00
Craig Topper
02d45efab2 [X86] Change all the i8imm operands in XOP instructions to u8imm so the parser will check the size. 
llvm-svn: 250147
 2015-10-13 05:06:25 +00:00
Simon Pilgrim
ebc177d6ad [X86][XOP] Added support for the lowering of 128-bit vector integer comparisons to XOP PCOM/PCOMU instructions. 
The XOP vector integer comparisons can deal with all signed/unsigned comparison cases directly and can be easily commuted as well (D7646).

llvm-svn: 249976
 2015-10-11 14:15:17 +00:00
Simon Pilgrim
d3e938c0f5 [X86][XOP] Added support for the lowering of 128-bit vector shifts to XOP shift instructions 
The XOP shifts just have logical/arithmetic versions and the left/right shifts are controlled by whether the value is positive/negative. Because of this I've added new X86ISD nodes instead of trying to force them to use the existing shift nodes.

Additionally Excavator cores (bdver4) support XOP and AVX2 - meaning that it should use the AVX2 shifts when it can and fall back to XOP in other cases.

Differential Revision: http://reviews.llvm.org/D8690

llvm-svn: 248878
 2015-09-30 08:17:50 +00:00
Simon Pilgrim
df7da0ee6e [X86][XOP] Enable commutation for XOP instructions 
Patch to allow XOP instructions (integer comparison and integer multiply-add) to be commuted. The comparison instructions sometimes require the compare mode to be flipped but the remaining instructions can use default commutation modes.

This patch also sets the SSE domains of all the XOP instructions.

Differential Revision: http://reviews.llvm.org/D7646

llvm-svn: 229267
 2015-02-14 22:40:46 +00:00
Craig Topper
3b9a8648f4 [X86] Add support for parsing and printing the mnemonic aliases for the XOP VPCOM instructions. 
llvm-svn: 229078
 2015-02-13 07:42:25 +00:00
Craig Topper
39e5a46fee [X86] Remove the remaining uses of memop from AVX and AVX2 instruction patterns. AVX and AVX2 can handle unaligned loads being folded so we can just use 'load' 
llvm-svn: 228551
 2015-02-08 22:38:25 +00:00
Craig Topper
75deac3bc2 Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field in TSFlags. 
llvm-svn: 200624
 2014-02-02 07:08:01 +00:00
Craig Topper
6fb0648c41 Add XOP disassembler support. Fixes PR13933. 
llvm-svn: 191874
 2013-10-03 05:17:48 +00:00
Craig Topper
7c37abcace Add explicit VEX_L tags to all 256-bit instructions. This will allow us to remove code from the code emitters that examined operands to set the L-bit. 
llvm-svn: 164202
 2012-09-19 06:06:34 +00:00
Craig Topper
b2299168d3 Fix intrinsics for XOP frczss/sd instructions. These instructions only take one source register and zero the upper bits of the destination rather than preserving them. 
llvm-svn: 158396
 2012-06-13 07:18:53 +00:00
Craig Topper
b355582afd Add intrinsics for immediate form of XOP vprot instructions. Use i128mem instead of f128mem for integer XOP instructions. 
llvm-svn: 158291
 2012-06-10 07:31:56 +00:00
Craig Topper
633e88fd15 Use XOP vpcom intrinsics in patterns instead of a target specific SDNode type. Remove the custom lowering code that selected the SDNode type. 
llvm-svn: 158279
 2012-06-09 17:02:24 +00:00
Jia Liu
6bb2f0f0e4 some comment fix for X86 and ARM 
llvm-svn: 150902
 2012-02-19 02:03:36 +00:00
Jia Liu
b077b6085d Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Craig Topper
c289726019 Remove most of the intrinsics for XOP VPCMOV instruction. They all aliased to the same instruction with different types. This would be better accomplished with casts in the not yet created xopintrin.h header file. 
llvm-svn: 149795
 2012-02-05 00:55:56 +00:00
Craig Topper
9aabdda961 Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic patterns with custom lowering to a target specific nodes. 
llvm-svn: 149216
 2012-01-30 01:10:15 +00:00
Craig Topper
8f8e428400 Add HasXOP predicate check covering a bunch of XOP intrinsic patterns. 
llvm-svn: 149054
 2012-01-26 07:51:55 +00:00
Jan Sjödin
cb98434ebe Add XOP Intrinsics and tests 
llvm-svn: 147949
 2012-01-11 15:20:20 +00:00
Craig Topper
b4db8689ee Add disassembler support for VPERMIL2PD and VPERMIL2PS. 
llvm-svn: 147368
 2011-12-30 06:23:39 +00:00
Craig Topper
44a5136fac Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. 
llvm-svn: 147366
 2011-12-30 04:48:54 +00:00
Jan Sjödin
b9e2da0d9a XOP instructions and encoding tests. 
llvm-svn: 146407
 2011-12-12 19:37:49 +00:00