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b284db0070
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8300 Commits

Author SHA1 Message Date
Manman Ren
b284db0070 Struct byval: use the correct alignment for loads generated to load 
from struct byval to registers.

We used to pass 0 which means the alignment of PtrVT. Even when the alignment
of the struct is smaller than 4, the LOADs would have alignment of 4, and
further optimizations could combine the LOADs into a ldm, which would
cause crash.

The fix is to pass the alignment of the struct byval.

rdar://problem/15144402

llvm-svn: 192126
 2013-10-07 19:47:53 +00:00
Benjamin Kramer
feace9b737 X86: Fix type check. Just because an integer type is illegal doesn't mean it's i64. 
Fixes PR17495, where an i24 triggered this code. It's intended to
optimize i64 loads on 32 bit x86.

llvm-svn: 192123
 2013-10-07 19:11:35 +00:00
Matt Arsenault
9c8541d286 Change objectsize intrinsic to accept different address spaces. 
Bitcasting everything to i8* won't work. Autoupgrade the old
intrinsic declarations to use the new mangling.

llvm-svn: 192117
 2013-10-07 18:06:48 +00:00
Amara Emerson
688cdc2151 [ARM] Improve build attributes emission. 
llvm-svn: 192111
 2013-10-07 16:55:23 +00:00
Chad Rosier
128d9134e7 [AArch64] Add support for NEON scalar arithmetic instructions: 
SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS.

llvm-svn: 192107
 2013-10-07 16:36:15 +00:00
Rafael Espindola
499aaf305a Add support for aliases with linkonce_odr. 
This will be used to extend constructor aliases in clang.

llvm-svn: 192066
 2013-10-06 15:10:43 +00:00
Benjamin Kramer
44710574cb Force a CPU that doesn't have AVX, otherwise this test fails. 
llvm-svn: 192065
 2013-10-06 13:52:41 +00:00
Benjamin Kramer
a7e734d765 X86: Don't fold spills into SSE operations if the stack is unaligned. 
Regalloc can emit unaligned spills nowadays, but we can't fold the
spills into SSE ops if we can't guarantee alignment. PR12250.

llvm-svn: 192064
 2013-10-06 13:48:22 +00:00
Elena Demikhovsky
cb8eaca2e4 AVX-512: added scalar convert instructions and intrinsics. 
Fixed load folding in VPERM2I instruction.

llvm-svn: 192063
 2013-10-06 13:11:09 +00:00
Venkatraman Govindaraju
2d62beab83 [Sparc] Do not emit nop after fcmp* instruction with V9. 
llvm-svn: 192056
 2013-10-06 07:06:44 +00:00
Elena Demikhovsky
0ff833ab99 AVX-512: fixed shuffle lowering 
in case of BLEND and added VSHUFPS patterns.

llvm-svn: 192055
 2013-10-06 06:11:18 +00:00
Venkatraman Govindaraju
aacd252702 [Sparc] Custom lower addc/adde/subc/sube on i64 in sparc64. 
This is required because i64 is a legal type but addxcc/subxcc reads icc carry bit, which are 32 bit conditional codes.

llvm-svn: 192054
 2013-10-06 03:36:18 +00:00
Venkatraman Govindaraju
fa75d8536b [Sparc] Use addxcc/subxcc for adde/sube instead of addx/subx. 
addx/subx does not modify conditional codes whereas addxcc/subxx does.

llvm-svn: 192053
 2013-10-06 02:11:10 +00:00
Benjamin Kramer
3a6afef4e7 Emit a better error when running out of registers on inline asm. 
The most likely case where this error happens is when the user specifies
too many register operands. Don't make it look like an internal LLVM bug
when we can see that the error is coming from an inline asm instruction.
For other instructions we keep the "ran out of registers" error.

llvm-svn: 192041
 2013-10-05 19:33:37 +00:00
Craig Topper
0a8f3fc996 Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns are sufficient. 
llvm-svn: 192039
 2013-10-05 19:22:59 +00:00
Craig Topper
d0a63f6722 Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into (sub -2, x). 
llvm-svn: 192037
 2013-10-05 17:17:53 +00:00
Jiangning Liu
6d9b4a0e25 Implement aarch64 neon instruction set AdvSIMD (Across). 
llvm-svn: 192028
 2013-10-05 08:22:10 +00:00
Rafael Espindola
86d473eceb Convert test to FileCheck. 
llvm-svn: 192025
 2013-10-05 02:58:36 +00:00
Venkatraman Govindaraju
179e7e6dea [Sparc] Use correct alignment while loading/storing fp128 values. 
llvm-svn: 192023
 2013-10-05 02:29:47 +00:00
Venkatraman Govindaraju
cf869e9b2a [Sparc] Respect hasHardQuad parameter correctly when lowering SINT_TO_FP with fp128 operand. 
llvm-svn: 192015
 2013-10-05 00:31:41 +00:00
Venkatraman Govindaraju
271e9485db [Sparc] Correct the floating point conditional code mapping in GetOppositeBranchCondition(). 
llvm-svn: 192006
 2013-10-04 23:54:30 +00:00
Reed Kotler
13ebdc7d9c Support tblockaddr for static compilation in Mips16. 
llvm-svn: 191986
 2013-10-04 22:01:40 +00:00
Akira Hatanaka
e85ca33e98 [mips] Fix a bug in MipsLongBranch::replaceBranch, which was erasing 
instructions in delay slots along with the original branch instructions.

llvm-svn: 191978
 2013-10-04 20:51:40 +00:00
Matthias Braun
f7ddf86363 ARM: optimizeSelect has to consider the previous register class 
optimizeSelect folds (predicated) copy instructions, it must not ignore
the original register class of the operand when replacing the register
with the copies dest register.

llvm-svn: 191963
 2013-10-04 16:52:56 +00:00
Matthias Braun
fbba53e45c ARM: do not add a regmask for TAILJUMPs 
The jump doesn't really kill the registers, the following call does but
we never get back anyway.
This avoids some verify-machineinstrs problems when TAILJUMPs are
if-converted.

llvm-svn: 191962
 2013-10-04 16:52:54 +00:00
Matthias Braun
ae6465eb28 ARM: preserve undef flag in pseudo instruction expanders 
Copy over the whole register machine operand instead of creating a new one
with an incomplete set of flags.

llvm-svn: 191961
 2013-10-04 16:52:51 +00:00
Jiangning Liu
9f33a743ab Implement aarch64 neon instruction set AdvSIMD (3V elem). 
llvm-svn: 191944
 2013-10-04 09:20:44 +00:00
Logan Chien
b51d0cd53b [arm] Enhance the test case by checking .fpu directive. 
llvm-svn: 191891
 2013-10-03 12:18:56 +00:00
Craig Topper
5b62ea95ec Remove duplicated test cases that occurred when I applied the same patch file to my model twice. 
llvm-svn: 191873
 2013-10-03 04:27:14 +00:00
Craig Topper
5ac188d0f2 Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. 
llvm-svn: 191871
 2013-10-03 04:16:45 +00:00
Elena Demikhovsky
ee11e148e9 AVX-512: fixed a bug in getLoadStoreRegOpcode() for AVX-512 target 
llvm-svn: 191818
 2013-10-02 12:20:42 +00:00
Vincent Lejeune
c7c1075d49 R600: add a pass that merges clauses. 
llvm-svn: 191790
 2013-10-01 19:32:58 +00:00
Vincent Lejeune
0321b7798e R600: Put PRED_X instruction in its own clause 
llvm-svn: 191789
 2013-10-01 19:32:49 +00:00
Vincent Lejeune
e0ac07a3cb R600: Enable -verify-machineinstrs in some tests. 
llvm-svn: 191788
 2013-10-01 19:32:38 +00:00
Preston Gurd
c52dfda610 Add test case for PR16785. 
Thanks for Dimitry Andric, Rafael Espindola, and Benjamin Kramer
for providing and progressively reducing the test case!

llvm-svn: 191782
 2013-10-01 17:02:48 +00:00
Richard Sandiford
8ac2bcbe80 [SystemZ] Add comparisons of high words and memory 
llvm-svn: 191777
 2013-10-01 15:00:44 +00:00
Richard Sandiford
2ed79fb1d7 [SystemZ] Add comparisons of large immediates using high words 
There are no corresponding patterns for small immediates because they would
prevent the use of fused compare-and-branch instructions.

llvm-svn: 191775
 2013-10-01 14:56:23 +00:00
Richard Sandiford
3b7b53e6f4 [SystemZ] Add immediate addition involving high words 
llvm-svn: 191774
 2013-10-01 14:53:46 +00:00
Richard Sandiford
884566de6e [SystemZ] Extend test-under-mask support to high GR32s 
llvm-svn: 191773
 2013-10-01 14:41:52 +00:00
Richard Sandiford
d2e34690a4 [SystemZ] Extend 32-bit RISBG optimizations to high words 
This involves using RISB[LH]G, whereas the equivalent z10 optimization
uses RISBG.

llvm-svn: 191770
 2013-10-01 14:36:20 +00:00
Richard Sandiford
e2f5332463 [SystemZ] Extend pseudo conditional 8- and 16-bit stores to high words 
As the comment says, we always want to use STOC for 32-bit stores.

llvm-svn: 191767
 2013-10-01 14:33:55 +00:00
Tim Northover
684a0e633d ARM: support interrupt attribute 
This function-attribute modifies the callee-saved register list and function
epilogue (specifically the return instruction) so that a routine is suitable
for use as an interrupt-handler of the specified type without disrupting
user-mode applications.

rdar://problem/14207019

llvm-svn: 191766
 2013-10-01 14:33:28 +00:00
Richard Sandiford
5df2380d20 [SystemZ] Add test missing from r191764. 
llvm-svn: 191765
 2013-10-01 14:31:50 +00:00
Richard Sandiford
7125240faa [SystemZ] Allow integer AND involving high words 
llvm-svn: 191762
 2013-10-01 14:20:41 +00:00
Richard Sandiford
9d3cacb101 [SystemZ] Allow integer XOR involving high words 
llvm-svn: 191759
 2013-10-01 14:08:44 +00:00
Richard Sandiford
d2a449d3de [SystemZ] Allow integer OR involving high words 
llvm-svn: 191755
 2013-10-01 13:22:41 +00:00
Richard Sandiford
3af32e8cab [SystemZ] Allow integer insertions with a high-word destination 
llvm-svn: 191753
 2013-10-01 13:18:56 +00:00
Richard Sandiford
497097c027 [SystemZ] Allow selects with a high-word destination 
llvm-svn: 191751
 2013-10-01 13:10:16 +00:00
Richard Sandiford
8c8e2f0237 [SystemZ] Add patterns to load a constant into a high word (IIHF) 
Similar to low words, we can use the shorter LLIHL and LLIHH if it turns
out that the other half of the GR64 isn't live.

llvm-svn: 191750
 2013-10-01 13:02:28 +00:00
Richard Sandiford
ac3360b004 [SystemZ] Add register zero extensions involving at least one high word 
llvm-svn: 191746
 2013-10-01 12:49:07 +00:00