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Commit Graph

41293 Commits

Author SHA1 Message Date
Duncan Sands
b2b5ddfaf6 Remove the MarkModRef pass (use AddReadAttrs instead).
Unfortunately this means removing one regression test
of GlobalsModRef because I couldn't work out how to
perform it without MarkModRef.

llvm-svn: 56342
2008-09-19 08:23:44 +00:00
Duncan Sands
c2ff9ca568 Add a new pass AddReadAttrs which works out which functions
can get the readnone/readonly attributes, and gives them it.
The plan is to remove markmodref (which did the same thing
by querying GlobalsModRef) and delete the analogous
functionality from GlobalsModRef.

llvm-svn: 56341
2008-09-19 08:17:05 +00:00
Duncan Sands
bb48df5839 Test the callgraph directly for the missing edge.
llvm-svn: 56338
2008-09-19 08:01:57 +00:00
Duncan Sands
aaa27f4261 Teach -callgraph to always print the callgraph (as the
description says it does), not just when -analyze is
used as well.  This means printing to stderr, so adjust
some tests.

llvm-svn: 56337
2008-09-19 07:57:09 +00:00
Dale Johannesen
214ddc92d0 Remove AsmThatEarlyClobber etc. from LiveIntervalAnalysis
and redo as linked list walk.  Logic moved into RA.
Per review feedback.

llvm-svn: 56326
2008-09-19 01:02:35 +00:00
Devang Patel
1e7ddf5d31 splitLoop does not handle split condition EQ.
Fixes PR 2805

llvm-svn: 56321
2008-09-18 23:45:14 +00:00
Dan Gohman
71b1f15917 Address-mode folding for X86FastISel. It's pretty basic, but it
catches a fair number of common cases. Note that this currently
causes Fast-ISel to leave behind lots of dead instructions.
Those will be dealt with in subsequent commits.

llvm-svn: 56320
2008-09-18 23:23:44 +00:00
Bill Wendling
aadf9b22a7 Decrementing the iterator here could be wrong if the worklist is empty after the "erase".
Thanks to Ji Young Park for the patch!

llvm-svn: 56316
2008-09-18 23:04:18 +00:00
Devang Patel
201223af46 Try to place hoisted instructions befoe icmp instruction.
llvm-svn: 56315
2008-09-18 22:50:42 +00:00
Evan Cheng
bcd694a1b4 Somehow RegAllocLinearScan is keeping two pointers to MachineRegisterInfo.
llvm-svn: 56314
2008-09-18 22:38:47 +00:00
Dan Gohman
e1c4ad399a Simplify this code. The FastISel class has its own TD member.
llvm-svn: 56311
2008-09-18 18:26:43 +00:00
Dan Gohman
9dc56fbe40 Don't consider instructions with implicit physical register
defs to be necessarily live.

llvm-svn: 56310
2008-09-18 18:22:32 +00:00
Tanya Lattner
e5fe7f7369 Upgrade doxygen.
llvm-svn: 56308
2008-09-18 16:32:28 +00:00
Dan Gohman
b7c5b0f44b Add a new "fast" scheduler. This is currently basically just a
copy of the BURRList scheduler, but with several parts ripped
out, such as backtracking, online topological sort maintenance
(needed by backtracking), the priority queue, and Sethi-Ullman
number computation and maintenance (needed by the priority
queue). As a result of all this, it generates somewhat lower
quality code, but that's its tradeoff for running about 30%
faster than list-burr in -fast mode in many cases.

This is somewhat experimental. Moving forward, major pieces of
this can be refactored with pieces in common with
ScheduleDAGRRList.cpp.

llvm-svn: 56307
2008-09-18 16:26:26 +00:00
Evan Cheng
a0459a1c5a Preliminary support for systems which require changing JIT memory regions privilege from read / write to read / executable.
llvm-svn: 56303
2008-09-18 07:54:21 +00:00
Evan Cheng
6acdef5d11 Duh. Default to ARMCC::AL (always).
llvm-svn: 56301
2008-09-18 07:28:19 +00:00
Evan Cheng
99a186e39f Clean up.
llvm-svn: 56300
2008-09-18 07:27:23 +00:00
Evan Cheng
b44e839f76 Cosmetic.
llvm-svn: 56299
2008-09-18 07:24:33 +00:00
Dan Gohman
5fbd0e95f3 FastISel: For calls, prefer using the callee's address as a constant
over having it in a register. And wait until after checking type
legality before requesting that the callee address be placed in a
register. Also, fix support for calls with void return type.

This speeds up fast-isel isel time by about 15% and reduces
instruction counts by about 3% overall on certain testcases. It also
changes many indirect calls to direct calls.

llvm-svn: 56292
2008-09-17 21:18:49 +00:00
Dale Johannesen
99091ed94f Add a bit to mark operands of asm's that conflict
with an earlyclobber operand elsewhere.  Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way 
that conflicts with an earlyclobber.  See also comments.

llvm-svn: 56290
2008-09-17 21:13:11 +00:00
Evan Cheng
d3225118a6 Unallocatable registers do not have live intervals.
llvm-svn: 56287
2008-09-17 18:36:25 +00:00
Devang Patel
88efee2dcc Do not hoist instruction above branch condition. The instruction may use branch condition.
llvm-svn: 56286
2008-09-17 18:21:49 +00:00
Devang Patel
50c22bf69b Do not ignore iv uses outside the loop.
This one slipped through cracks very well.

llvm-svn: 56284
2008-09-17 17:53:47 +00:00
Devang Patel
f08b10b15d Fix comments, help messages.
llvm-svn: 56282
2008-09-17 16:01:39 +00:00
Dan Gohman
4bef47e8c3 Don't worry about clobbering physical register defs that aren't used.
llvm-svn: 56281
2008-09-17 15:25:49 +00:00
Evan Cheng
f2c04a10e6 Fix addrmode1 instruction encodings; fix bx_ret encoding.
llvm-svn: 56277
2008-09-17 07:53:38 +00:00
Evan Cheng
d268288d39 Specify instruction encoding using range list to avoid endianess issues.
llvm-svn: 56276
2008-09-17 07:16:21 +00:00
Evan Cheng
b3923fd86f Add instruction names as comments to InstBits entries.
llvm-svn: 56275
2008-09-17 06:29:52 +00:00
Dan Gohman
9475c22537 Simplify and generalize X86DAGToDAGISel::CanBeFoldedBy, and draw
up some new ascii art to illustrate what it does. This change
currently has no effect on generated code.

llvm-svn: 56270
2008-09-17 01:39:10 +00:00
Dan Gohman
d0c6cb65e8 Add a new MachineInstr-level DCE pass. It is very simple, and is intended to
be used with fast-isel.

llvm-svn: 56268
2008-09-17 00:43:24 +00:00
Bill Wendling
b2701e541c Add trampoline support to PPC. GCC simply calls the "__trampoline_setup"
function with appropriate parameters. This allows us to support blocks on PPC.

llvm-svn: 56267
2008-09-17 00:30:57 +00:00
Devang Patel
65b85f3049 Fix cut-n-pasto.
llvm-svn: 56265
2008-09-17 00:01:04 +00:00
Evan Cheng
6cfbecd1fa When converting a CopyFromReg to a copy instruction, use the register class of its uses to determine the right destination register class of the copy. This is important for targets where a physical register may belong to multiple register classes.
llvm-svn: 56258
2008-09-16 23:12:11 +00:00
Devang Patel
7267b480ef Remove.
llvm-svn: 56256
2008-09-16 22:26:44 +00:00
Devang Patel
e2702c8994 Add -O1, -O2 and -O3 that matches llvm-gcc's -O1, -O2 and -O3 respectively.
llvm-svn: 56255
2008-09-16 22:25:14 +00:00
Dan Gohman
9cbb3f591a Change SelectionDAG::getConstantPool to always set the alignment of the
ConstantPoolSDNode, using the target's preferred alignment for the
constant type.

In LegalizeDAG, when performing loads from the constant pool, the
ConstantPoolSDNode's alignment is used in the calls to getLoad and
getExtLoad.

This change prevents SelectionDAG::getLoad/getExtLoad from incorrectly
choosing the ABI alignment for constant pool loads when Alignment == 0.
The incorrect alignment is only a performance issue when ABI alignment
does not equal preferred alignment (i.e., on x86 it was generating
MOVUPS instead of MOVAPS for v4f32 constant loads when the default ABI
alignment for 128bit vectors is forced to 1 byte.)

Patch by Paul Redmond!

llvm-svn: 56253
2008-09-16 22:05:41 +00:00
Bill Wendling
932818c75a Reverting r56249. On further investigation, this functionality isn't needed.
Apologies for the thrashing.

llvm-svn: 56251
2008-09-16 21:48:12 +00:00
Dan Gohman
6da3227304 Include the alignment value when displaying ConstantPoolSDNodes.
llvm-svn: 56250
2008-09-16 21:18:22 +00:00
Bill Wendling
1a240c8033 - Change "ExternalSymbolSDNode" to "SymbolSDNode".
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol

These changes pave the way to allowing SymbolSDNodes with non-external linkage.

llvm-svn: 56249
2008-09-16 21:12:30 +00:00
Dan Gohman
f89b35c261 Fix these comments to reflect current reality. Surprisingly,
MachineConstantPool::getConstantPoolIndex actually expects
a log2-encoded alignment.

llvm-svn: 56248
2008-09-16 20:45:53 +00:00
Dan Gohman
885e592e9b Finally re-apply r46959. This is made feasible by the combination
of r56230, r56232, and r56246.

llvm-svn: 56247
2008-09-16 18:52:57 +00:00
Dan Gohman
c598e29a1c Improve instcombine's handling of integer min and max in two ways:
- Recognize expressions like "x > -1 ? x : 0" as min/max and turn them
   into expressions like "x < 0 ? 0 : x", which is easily recognizable
   as a min/max operation.
 - Refrain from folding expression like "y/2 < 1" to "y < 2" when the
   comparison is being used as part of a min or max idiom, like
   "y/2 < 1 ? 1 : y/2". In that case, the division has another use, so
   folding doesn't eliminate it, and obfuscates the min/max, making it
   harder to recognize as a min/max operation.

These benefit ScalarEvolution, CodeGen, and anything else that wants to
recognize integer min and max.

llvm-svn: 56246
2008-09-16 18:46:06 +00:00
Evan Cheng
f80fc084ef AllocateRWXMemory -> AllocateRWX.
llvm-svn: 56244
2008-09-16 17:28:18 +00:00
Dan Gohman
d987c8990c FCmpInst predicates UNO, ORD, FALSE, and TRUE are commutative.
llvm-svn: 56243
2008-09-16 16:44:00 +00:00
Bill Wendling
fe6f2228ab Fix test to account for no more whitespace and that one of the matches is the
"declare" statement.

llvm-svn: 56241
2008-09-16 06:40:04 +00:00
Bill Wendling
f9a01704af Remove space that was forgotten.`
llvm-svn: 56240
2008-09-16 06:30:47 +00:00
Dan Gohman
37457ca74b Don't take the time to CheckDAGForTailCallsAndFixThem when tail calls
are not enabled. Instead just omit the tail call flag when calls are
created.

llvm-svn: 56235
2008-09-16 01:42:28 +00:00
Dan Gohman
64622ff4d6 Fix spacing in the grep line for this test, following the recent
SCEV-whitespace changes.

llvm-svn: 56234
2008-09-16 01:37:08 +00:00
Dan Gohman
54ef20348e Re-enables the new vector select in the bitcode reader, by modifying the
bitcode reader/writer as follows:

- add and use new bitcode FUNC_CODE_INST_VSELECT to handle the llvm
select opcode using either i1 or [N x i1] as the selector.
- retain old BITCODE FUNC_CODE_INST_SELECT in the bitcode reader to
handle select on i1 for backwards compatibility with existing bitcode
files.
- re-enable the vector-select.ll test program.

Also, rename the recently added bitcode opcode FUNC_CODE_INST_VCMP to
FUNC_CODE_INST_CMP2 and make the bitcode writer use it to handle
fcmp/icmp on scalars or vectors. In the bitcode writer, use
FUNC_CODE_INST_CMP for vfcmp/vicmp only. In the bitcode reader, have
FUNC_CODE_INST_CMP handle icmp/fcmp returning bool, for backwards
compatibility with existing bitcode files.

Patch by Preston Gurd!

llvm-svn: 56233
2008-09-16 01:01:33 +00:00
Dan Gohman
0045cec2ba Teach ScalarEvolution to consider loop preheaders in the search for
an if statement that guards a loop, to allow indvars to avoid smax
operations in more situations.

llvm-svn: 56232
2008-09-15 22:18:04 +00:00