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Commit Graph

163090 Commits

Author SHA1 Message Date
Sean Fertile
b36844592b [PartialInlining] Fix Crash from holding a reference to a destructed ORE.
The callback used to create an ORE for the legacy PI pass caches the allocated
object in a unique_ptr in the runOnModule function, and returns a reference to
that object. Under certian circumstances we can end up holding onto that
reference after the OREs destruction. Rather then allowing the new and legacy
passes to create ORE object in diffrent ways, create the ORE at the point of
use.

Differential Revision: https://reviews.llvm.org/D43219

llvm-svn: 330473
2018-04-20 19:56:26 +00:00
Krzysztof Parzyszek
06942e2447 [Hexagon] hexagon-autohvx was left on again
llvm-svn: 330472
2018-04-20 19:45:49 +00:00
Krzysztof Parzyszek
9c83713b22 [Hexagon] Improve HVX instruction selection (bitcast, vsplat)
There was some unfortunate interaction between VSPLAT and BITCAST
related to the selection of constant vectors (coming from selecting
shuffles). Introduce VSPLATW that always splats a 32-bit word, and
can have arbitrary result type (to avoid BITCASTs of VSPLAT).
Clean up the previous selection of BITCAST/VSPLAT.

llvm-svn: 330471
2018-04-20 19:38:37 +00:00
Eric Christopher
9e3701d460 Remove unused argument from emitModuleMetadata.
NFCI.

llvm-svn: 330470
2018-04-20 19:07:57 +00:00
Krzysztof Parzyszek
d46b725fba [Hexagon] Skip fixed-stack indexes in HexagonConstExtenders
Fixed slots have negative values, and TRI::stackSlot2Index and
TRI::index2StackSlot do not handle negative numbers.

llvm-svn: 330468
2018-04-20 19:06:46 +00:00
Craig Topper
c6659fbed4 [X86][SandyBridge] Remove duplciate InstRWs from Sandy Brige scheduler model.
llvm-svn: 330465
2018-04-20 18:55:40 +00:00
Gabor Buella
f08c51f224 [X86] WaitPKG instructions
Three new instructions:

umonitor - Sets up a linear address range to be
monitored by hardware and activates the monitor.
The address range should be a writeback memory
caching type.

umwait - A hint that allows the processor to
stop instruction execution and enter an
implementation-dependent optimized state
until occurrence of a class of events.

tpause - Directs the processor to enter an
implementation-dependent optimized state
until the TSC reaches the value in EDX:EAX.

Also modifying the description of the mfence
instruction, as the rep prefix (0xF3) was allowed
before, which would conflict with umonitor during
disassembly.

Before:
$ echo 0xf3,0x0f,0xae,0xf0 | llvm-mc -disassemble
.text
mfence

After:
$ echo 0xf3,0x0f,0xae,0xf0 | llvm-mc -disassemble
.text
umonitor        %rax

Reviewers: craig.topper, zvi

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D45253

llvm-svn: 330462
2018-04-20 18:42:47 +00:00
Jessica Paquette
c755676edc [MachineOutliner] Change B instruction for tail calls to TCRETURNdi
First off, this is more correct than having the B. Second off, this was making
a bot upset. This fixes that.

Update the test to include -verify-machineinstrs as well to prevent stuff like
this slipping by non debug/assert builds in the future.

llvm-svn: 330459
2018-04-20 18:03:21 +00:00
Zachary Turner
ae6e38e5af [LLD/PDB] Emit first section contribution for DBI Module Descriptor.
Part of the DBI stream is a list of variable length structures
describing each module that contributes to the final executable.

One member of this structure is a section contribution entry that
describes the first section contribution in the output file for
the given module.

We have been leaving this structure unpopulated until now, so with
this patch it is now filled out correctly.

Differential Revision: https://reviews.llvm.org/D45832

llvm-svn: 330457
2018-04-20 18:00:46 +00:00
Nico Weber
f8d747bd3f Remove llvm-build's --configure-target-def-file.
It was added 6.5 years ago in r144345, but was never hooked up and has been
unused since.  If _you_ do use this, feel free to revert, but add a comment
on where it's used.

https://reviews.llvm.org/D45262

llvm-svn: 330455
2018-04-20 17:21:10 +00:00
Sanjay Patel
f5e87f5e16 [utils] improve AArch64 asm parser
If we don't mark the cfi line as optional, the script won't
work with 'nounwind' code. Without that attr, there may be
extra noise in the asm body that we don't want to see.

llvm-svn: 330453
2018-04-20 17:16:23 +00:00
Nicholas Wilson
0827c45cc6 [WebAssembly] Distinguish debug/symbol names in the Wasm structs. NFC
Differential Revision: https://reviews.llvm.org/D45021

llvm-svn: 330448
2018-04-20 17:07:24 +00:00
Michael Zolotukhin
af04276c02 Revert r330431.
There are still stage3/stage4 miscompares :(

llvm-svn: 330446
2018-04-20 16:57:10 +00:00
Sanjay Patel
ed4be957b0 [x86] auto-generate checks; NFC
There's a proposal to change/add to this file in D45653,
so we should know exactly what those differences would be. 

llvm-svn: 330445
2018-04-20 16:46:58 +00:00
Florian Hahn
39281bf454 [NewGVN] Split OpPHI detection and creation.
It also adds a check making sure PHIs for operands are all in the same
block.

Patch by Daniel Berlin <dberlin@dberlin.org>

Reviewers: dberlin, davide

Differential Revision: https://reviews.llvm.org/D43865

llvm-svn: 330444
2018-04-20 16:37:13 +00:00
Andrew Ng
8dc720bb33 [DebugInfo] Use WithColor for more debug line warnings
Updated two more debug line related warnings to use WithColor. This was
necessary to ensure consistent output order of the warnings on Windows
for debug line tests.

Differential Revision: https://reviews.llvm.org/D45871

llvm-svn: 330440
2018-04-20 15:29:47 +00:00
Simon Pilgrim
5cb0cef17d [CostModel][X86] Add vector element insert/extract cost tests
llvm-svn: 330439
2018-04-20 15:26:59 +00:00
Douglas Yung
e555ec18b3 Fix test by allowing it to accept an upper or lower case letter as the first character.
Windows for some reason uses a lower case letter, while linux uses upper case.

llvm-svn: 330438
2018-04-20 15:23:57 +00:00
Sanjay Patel
093a966fb5 [DAGCombine] (float)((int) f) --> ftrunc (PR36617)
This was originally committed at rL328921 and reverted at rL329920 to
investigate failures in Chrome. This time I've added to the ReleaseNotes
to warn users of the potential of exposing UB and let me repeat that
here for more exposure:

  Optimization of floating-point casts is improved. This may cause surprising
  results for code that is relying on undefined behavior. Code sanitizers can
  be used to detect affected patterns such as this:

    int main() {
      float x = 4294967296.0f;
      x = (float)((int)x);
      printf("junk in the ftrunc: %f\n", x);
      return 0;
    }

    $ clang -O1 ftrunc.c -fsanitize=undefined ; ./a.out
    ftrunc.c:5:15: runtime error: 4.29497e+09 is outside the range of 
                   representable values of type 'int'
    junk in the ftrunc: 0.000000


Original commit message:

fptosi / fptoui round towards zero, and that's the same behavior as ISD::FTRUNC,
so replace a pair of casts with the equivalent node. We don't have to account for
special cases (NaN, INF) because out-of-range casts are undefined.

Differential Revision: https://reviews.llvm.org/D44909

llvm-svn: 330437
2018-04-20 15:07:55 +00:00
Simon Pilgrim
a0c94d4135 [CostModel][X86] Add srem/urem constant cost tests
llvm-svn: 330436
2018-04-20 15:01:03 +00:00
Simon Pilgrim
41555f90b1 [CostModel][X86] Add SLM/GLM/BtVer2 compare + division/remainder cost tests
llvm-svn: 330435
2018-04-20 14:50:34 +00:00
Michael Zolotukhin
dd4ddf9464 Fix typo in a test.
llvm-svn: 330434
2018-04-20 13:51:36 +00:00
Simon Pilgrim
84ede8df3f [CostModel][X86] Split off BtVer2 cost checks
llvm-svn: 330433
2018-04-20 13:50:33 +00:00
Simon Pilgrim
fb65b6cc82 [CostModel][X86] Add GoldmontPlus cost tests
Just reuses goldmont costs atm

llvm-svn: 330432
2018-04-20 13:42:53 +00:00
Michael Zolotukhin
ece1dc32fe Revert "Revert r330403 and r330413."
Reapply the patches with a fix. Thanks Ilya and Hans for the reproducer!
This reverts commit r330416.

The issue was that removing predecessors invalidated uses that we stored
for rewrite. The fix is to finish manipulating with CFG before we select
uses for rewrite.

llvm-svn: 330431
2018-04-20 13:34:32 +00:00
Simon Pilgrim
3aaec060ee [X86][BtVer2] Cleanup some old FIXMEs from the model. NFCI.
llvm-svn: 330428
2018-04-20 13:12:04 +00:00
Simon Pilgrim
404cf2b1bb [X86] Tag CLDEMOTE instruction with WriteLoad scheduling class
Same as other cacheline instructions

llvm-svn: 330424
2018-04-20 12:54:53 +00:00
Sander de Smalen
b22701bd85 [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load instructions.
This is patch [4/4] in a series to add assembler/disassembler support for
SVE's contiguous LD1 (scalar+scalar) instructions:
- Patch [1/4]: https://reviews.llvm.org/D45687
- Patch [2/4]: https://reviews.llvm.org/D45688
- Patch [3/4]: https://reviews.llvm.org/D45689
- Patch [4/4]: https://reviews.llvm.org/D45690

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D45690

llvm-svn: 330423
2018-04-20 12:52:01 +00:00
Jonas Devlieghere
c0a6317d37 [ObjectYAML] Add ability for DWARFYAML to calculate DIE lengths
This patch adds the ability for the ObjectYAML DWARFEmitter to calculate
the lengths of DIEs. This is accomplished by creating a DIEFixupVisitor
class which traverses the DWARF DIEs to calculate and fix up the lengths
in the Compile Unit header.

The DIEFixupVisitor can be extended in the future to enable more complex
fix ups which will enable simplified YAML string representations.

This is also very useful when using the YAML format in unit tests
because you no longer need to know the length of the compile unit when
writing the YAML string.

Differential commandeered from Chris Bieneman (beanz)

Differential revision: https://reviews.llvm.org/D30666

llvm-svn: 330421
2018-04-20 12:33:49 +00:00
Greg Bedwell
312638e5f5 [UpdateTestChecks] Fix update_mca_test_checks.py slowness issue
The script was using Python's difflib module to calculate the number of
lines changed so that it could report it in its status output.  It turns
out this can be very very slow on large sets of lines (Python bug 6931).
It's not worth the cost, so just remove the usage of difflib entirely.

llvm-svn: 330419
2018-04-20 11:38:11 +00:00
Florian Hahn
3d5c366127 Require asserts for stats-file-option tests.
llvm-svn: 330417
2018-04-20 11:21:13 +00:00
Ilya Biryukov
9e434daed5 Revert r330403 and r330413.
Revert r330413: "[SSAUpdaterBulk] Use SmallVector instead of DenseMap for storing rewrites."
Revert r330403 "Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." one more time."

r330403 commit seems to crash clang during our integrate while doing PGO build with the following stacktrace:
      #2 llvm::SSAUpdaterBulk::RewriteAllUses(llvm::DominatorTree*, llvm::SmallVectorImpl<llvm::PHINode*>*)
      #3 llvm::JumpThreadingPass::ThreadEdge(llvm::BasicBlock*, llvm::SmallVectorImpl<llvm::BasicBlock*> const&, llvm::BasicBlock*)
      #4 llvm::JumpThreadingPass::ProcessThreadableEdges(llvm::Value*, llvm::BasicBlock*, llvm::jumpthreading::ConstantPreference, llvm::Instruction*)
      #5 llvm::JumpThreadingPass::ProcessBlock(llvm::BasicBlock*)
The crash happens while compiling 'lib/Analysis/CallGraph.cpp'.

r3340413 is reverted due to conflicting changes.

llvm-svn: 330416
2018-04-20 10:52:54 +00:00
Roman Lebedev
28dcce4f97 [NFC][InstCombine] Regenerate two tests that are affected by folding masked merge
llvm-svn: 330415
2018-04-20 10:49:19 +00:00
Andrew Ng
5145f7f5f7 [DebugInfo] Fix for split dwarf test on Windows (NFC)
On Windows, %llc_dwarf automatically adds -mtriple causing this test to
error. Changed %llc_dwarf to llc.

Differential Revision: https://reviews.llvm.org/D45869

llvm-svn: 330414
2018-04-20 10:44:42 +00:00
Michael Zolotukhin
c7d8ceacbd [SSAUpdaterBulk] Use SmallVector instead of DenseMap for storing rewrites.
llvm-svn: 330413
2018-04-20 10:31:06 +00:00
Ilya Biryukov
30ee746f6f [Dockerfiles] Split checkout and build scripts into separate files.
Summary:
This is a small refactoring to extract the svn checkout code from the
build script used inside the docker image.
This would give more flexibility if more than a single invocation of
cmake is needed inside the docker image.

User-facing interface (build_docker_image.sh) hasn't changed, only the
internal scripts running inside the build container are affected.

Reviewers: ioeric

Reviewed By: ioeric

Subscribers: mehdi_amini, llvm-commits

Differential Revision: https://reviews.llvm.org/D45868

llvm-svn: 330412
2018-04-20 10:19:38 +00:00
Florian Hahn
dd48f29ba7 [LTO] Add stats-file option to LTO/Config.h.
This patch adds a StatsFile option to LTO/Config.h and updates both
LLVMGold and llvm-lto2 to set it.

Reviewers: MatzeB, tejohnson, espindola

Reviewed By: tejohnson

Differential Revision: https://reviews.llvm.org/D45531

llvm-svn: 330411
2018-04-20 10:18:36 +00:00
Andrea Di Biagio
4a6b22b91f CODE_OWNERS: Take code ownership of llvm-mca.
llvm-svn: 330410
2018-04-20 10:16:31 +00:00
Dan Liew
63cbec945c [lit] Fix a bug where UNRESOLVED tests were not handled in the XUnit
XML printer.

A test has been added that tries to comprehensively test emitting
XUnit XML output for shell tests.

Differential Revision: https://reviews.llvm.org/D45567

llvm-svn: 330409
2018-04-20 10:11:41 +00:00
Sander de Smalen
faa1097556 [AArch64][SVE] Fix diagnostic for SVE LD4 instructions:
Diagnostic:
  'index must be multiple of 3 in range [-32, 28]'

Must be:
  'index must be multiple of 4 in range [-32, 28]'

llvm-svn: 330407
2018-04-20 09:45:50 +00:00
Sander de Smalen
e3d2d2d1b1 [AArch64][SVE] Added GPR64shifted and GPR64NoXZRshifted register classes.
Summary:
This is patch [3/4] in a series to add assembler/disassembler support for
SVE's contiguous LD1 (scalar+scalar) instructions:
- Patch [1/4]: https://reviews.llvm.org/D45687
- Patch [2/4]: https://reviews.llvm.org/D45688
- Patch [3/4]: https://reviews.llvm.org/D45689
- Patch [4/4]: https://reviews.llvm.org/D45690

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: SjoerdMeijer

Subscribers: tschuett, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45689

llvm-svn: 330406
2018-04-20 08:54:49 +00:00
Michael Zolotukhin
63a8cb37da Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." one more time.
Hopefully, changing set to vector removes nondeterminism detected by
some bots, or the new assert will catch something.

This reverts commit r330180.

llvm-svn: 330403
2018-04-20 08:01:08 +00:00
Michael Zolotukhin
8f37fad065 [SSAUpdaterBulk] Add an assert.
llvm-svn: 330402
2018-04-20 07:59:57 +00:00
Daniel Cederman
7415ad946f Add SPARC support to update_llc_test_checks.py
Reviewers: spatel, jyknight

Reviewed By: spatel

Subscribers: fedor.sergeev, llvm-commits

Differential Revision: https://reviews.llvm.org/D45809

llvm-svn: 330401
2018-04-20 07:59:13 +00:00
Michael Zolotukhin
9a465a9cac [SSAUpdaterBulk] Add * and & to auto.
llvm-svn: 330400
2018-04-20 07:58:54 +00:00
Michael Zolotukhin
14e2309a1f [SSAUpdaterBulk] Use PredCache in ComputeLiveInBlocks.
llvm-svn: 330399
2018-04-20 07:57:24 +00:00
Michael Zolotukhin
9cf7e64978 [SSAUpdaterBulk] Use SmallVector instead of SmallPtrSet for uses.
llvm-svn: 330398
2018-04-20 07:56:00 +00:00
Daniel Cederman
4f1d3f2563 Revert "This pass, fixing an erratum in some LEON 2 processors..."
Summary:
Reading Atmel's AT697E errata document this does not seem like a valid
workaround. While the text only mentions SDIV, it says that the ICC flags
can be wrong, and those are only generated by SDIVcc. Verification on
hardware shows that simply replacing SDIV with SDIVcc does not avoid
the bug with negative operands.

This reverts r283727.

Reviewers: lero_chris, jyknight

Reviewed By: jyknight

Subscribers: fedor.sergeev, jrtc27, llvm-commits

Differential Revision: https://reviews.llvm.org/D45813

llvm-svn: 330397
2018-04-20 07:53:27 +00:00
Daniel Cederman
cfc303a827 [Sparc] Use synthetic instruction clr to zero register instead of sethi
Using `clr reg`/`mov %g0, reg`/`or %g0, %g0, reg` to zero a register
looks much better than `sethi 0, reg`.

Reviewers: jyknight, venkatra

Reviewed By: jyknight

Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits

Differential Revision: https://reviews.llvm.org/D45810

llvm-svn: 330396
2018-04-20 07:47:12 +00:00
Sander de Smalen
1913ea25b4 [AArch64][AsmParser] Extend RegOp with integrated 'shift/extend'.
Summary:
In some cases the shift/extend needs to be explicitly parsed together
with the register, rather than as a separate operand. This is needed
for addressing modes where the instruction as a whole dictates the
scaling/extend, rather than specific bits in the instruction.
By parsing them as a single operand, we avoid the need to pass an
extra operand in all CodeGen patterns (because all operands need to
have an associated value), and we avoid the need to update TableGen to
accept operands that have no associated bits in the instruction.

An added benefit of parsing them together is that the assembler
can give a sensible diagnostic if the scaling is not correct.

This is patch [2/4] in a series to add assembler/disassembler support for
SVE's contiguous LD1 (scalar+scalar) instructions:
- Patch [1/4]: https://reviews.llvm.org/D45687
- Patch [2/4]: https://reviews.llvm.org/D45688
- Patch [3/4]: https://reviews.llvm.org/D45689
- Patch [4/4]: https://reviews.llvm.org/D45690

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: fhahn, SjoerdMeijer

Subscribers: kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45688

llvm-svn: 330394
2018-04-20 07:24:20 +00:00