RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-01 16:33:37 +01:00
Code Issues Projects Releases Wiki Activity
80,761 Commits 4 Branches 5 Tags 704 MiB
b41a7a21e6
Commit Graph

80761 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Jim Grosbach
dbeec050c2 ARM pre-v6 alias for 'nop' to 'mov r0, r0' 
llvm-svn: 152185
 2012-03-07 00:52:41 +00:00
Jim Grosbach
9ef7f069b5 Tidy up. Remove dead code that slipped into previous commit. 
llvm-svn: 152184
 2012-03-07 00:52:39 +00:00
Andrew Trick
a87bfe64ad Added -view-background to avoid waiting for each GraphViz invocation. 
GV and XDOT paths are untested but should work the same.

llvm-svn: 152179
 2012-03-07 00:18:27 +00:00
Andrew Trick
b400cf42a4 Added -view-misched=dags options. 
llvm-svn: 152178
 2012-03-07 00:18:25 +00:00
Andrew Trick
8474910b42 Cleanup in preparation for misched: Move DAG visualization logic. 
Soon, ScheduleDAG will not refer to the BB.

llvm-svn: 152177
 2012-03-07 00:18:22 +00:00
Andrew Trick
d35b75a36c Added MachineBasicBlock::getFullName() to standardize/factor codegen diagnostics. 
llvm-svn: 152176
 2012-03-07 00:18:18 +00:00
Andrew Trick
e06a3f8642 whitespace 
llvm-svn: 152175
 2012-03-07 00:18:15 +00:00
Andrew Trick
1fb15f4f48 Cleanup: DAG building is specific to either SD or MI scheduling. Not part of the target interface. 
llvm-svn: 152174
 2012-03-07 00:18:12 +00:00
Andrew Trick
80ff2f2d36 misched comments 
llvm-svn: 152173
 2012-03-07 00:18:08 +00:00
Andrew Trick
0f29eb5ff1 misched: Use the StartBlock/FinishBlock hooks 
llvm-svn: 152172
 2012-03-07 00:18:05 +00:00
Eric Christopher
6d5c7a5141 Add the DW_AT_APPLE_runtime_class attribute to forward declarations 
as well as completely defined classes.

This fixes rdar://10956070

llvm-svn: 152171
 2012-03-07 00:15:19 +00:00
Evan Cheng
f04f2e7a52 Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation). 
llvm-svn: 152162
 2012-03-06 23:33:32 +00:00
Jim Grosbach
3b5f99f716 ARM more NEON VLD/VST composite physical register refactoring. 
Register pair, all lanes subscripting.

llvm-svn: 152157
 2012-03-06 23:10:38 +00:00
Jakob Stoklund Olesen
b29383fc6a Hoist common code out of if statement. 
llvm-svn: 152153
 2012-03-06 22:27:13 +00:00
Jim Grosbach
a3eeee8a91 ARM refactor more NEON VLD/VST instructions to use composite physregs 
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.

llvm-svn: 152150
 2012-03-06 22:01:44 +00:00
Owen Anderson
7bc84e0b4b Fix support for encodings up to 64-bits in length. TableGen was silently truncating them to 32-bits prior to this. 
llvm-svn: 152148
 2012-03-06 21:48:32 +00:00
Benjamin Kramer
0637e87d74 SmallPtrSet: Provide a more efficient implementation of swap than the default triple-copy std::swap. 
This currently assumes that both sets have the same SmallSize to keep the implementation simple,
a limitation that can be lifted if someone cares.

llvm-svn: 152143
 2012-03-06 20:40:02 +00:00
Eli Friedman
c397259ea6 Fix the operand ordering on aliases for shld and shrd. PR12173, part 2. 
llvm-svn: 152136
 2012-03-06 19:58:46 +00:00
Ted Kremenek
b98ec7f4ed Add new load commands for MachO. 
llvm-svn: 152135
 2012-03-06 19:54:44 +00:00
Daniel Dunbar
43586c3964 build/Darwin: Make it easy to cause all tools to get codesigned (with make CODESIGN_TOOLS=1). 
- On OS X 10.7+ this is apparently recommended practice. This maybe should
   become a configurey thing one day, but I'm not sure it is right to
   automatically turn it on.

llvm-svn: 152133
 2012-03-06 19:07:38 +00:00
Jim Grosbach
63e971ffae Tidy up. Kill some dead code. 
llvm-svn: 152131
 2012-03-06 18:59:19 +00:00
Jakob Stoklund Olesen
f772e5e379 Allow the same types in DPair as in QPR. 
llvm-svn: 152129
 2012-03-06 18:44:11 +00:00
Kevin Enderby
64d11852dd Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction. 
llvm-svn: 152127
 2012-03-06 18:33:12 +00:00
Roman Divacky
9bfd7cd1ad Convert PowerPC to register mask operands. 
llvm-svn: 152122
 2012-03-06 16:41:49 +00:00
Benjamin Kramer
2303c94eb1 Remove excess const, a const_iterator shouldn't be const itself. 
Fixes 1242 warnings from gcc during clang build.

llvm-svn: 152120
 2012-03-06 13:32:36 +00:00
Jay Foad
f7931a878d Change ConstantAggrUniqueMap to use Chandler's new hashing 
implementation. Patch by Meador Inge

llvm-svn: 152116
 2012-03-06 10:43:52 +00:00
Bill Wendling
2e6d007434 Add column width. 
llvm-svn: 152115
 2012-03-06 09:23:25 +00:00
Bill Wendling
21eade38c2 Remove short tag marker. 
llvm-svn: 152114
 2012-03-06 09:22:03 +00:00
Bill Wendling
b04d2f31ce Appease the HTML validation gods. 
llvm-svn: 152113
 2012-03-06 09:20:59 +00:00
Bill Wendling
20e20f4af0 Fix validation errors. 
llvm-svn: 152112
 2012-03-06 09:17:39 +00:00
Bill Wendling
14bc5fe306 Fix validation errors. 
llvm-svn: 152111
 2012-03-06 09:17:04 +00:00
Bill Wendling
cd79906a9b Add missing end tags. 
llvm-svn: 152110
 2012-03-06 08:59:13 +00:00
Argyrios Kyrtzidis
c919e757e2 [TinyPtrVector] Add erase method and const-goodness. 
llvm-svn: 152107
 2012-03-06 07:14:58 +00:00
Argyrios Kyrtzidis
267b14e42c PointerUnion::getAddrOf() does not need to be template since we can only 
use the first pointer type for it. Rename it to getAddrOfPtr1().

llvm-svn: 152106
 2012-03-06 07:14:54 +00:00
Craig Topper
86f61a903c Use uint16_t to store indices into string table since C++ only allows 64K string literals so the index into the big string can never be larger than that. 
llvm-svn: 152105
 2012-03-06 06:04:39 +00:00
Craig Topper
7efb0c3034 Add asserts to ensure that values will fit into the tables. 
llvm-svn: 152104
 2012-03-06 04:39:52 +00:00
Craig Topper
723f98cc58 Increase number of allowed registers in register classes to 64k instead of 256. Widen register class ID to 16-bits. Widen register size and alignment to be up to 64k bytes instead of 256 bytes. This partially reverts r152019 to be less restrictive. 
llvm-svn: 152100
 2012-03-06 03:44:22 +00:00
Craig Topper
ab4842ceda Revert r152016 and allow overlap, sub, super register tables to be more than 64k entries. 
llvm-svn: 152099
 2012-03-06 03:28:45 +00:00
Argyrios Kyrtzidis
e07aa2dee3 Remove UsuallyTinyPtrVector. 
It is just a worse version of TinyPtrVector.

llvm-svn: 152097
 2012-03-06 03:02:16 +00:00
Jakob Stoklund Olesen
d4e1cb591a Add <imp-def> operands when reloading into physregs. 
When an instruction only writes sub-registers, it is still necessary to
add an <imp-def> operand for the super-register.  When reloading into a
virtual register, rewriting will add the operand, but when loading
directly into a virtual register, the <imp-def> operand is still
necessary.

llvm-svn: 152095
 2012-03-06 02:48:17 +00:00
Eric Christopher
fec0accf3d Fix up link and a couple small edits. 
llvm-svn: 152094
 2012-03-06 02:25:41 +00:00
Eric Christopher
258d2080f5 Add the beginnings of documentation for the Name Accelerator Tables. 
Based on a writeup originally by Greg Clayton.

Abuse div and pre tags horribly. Needs a bit more cleanup.

llvm-svn: 152093
 2012-03-06 02:25:38 +00:00
Eric Christopher
7e92b59264 Delete trailing whitespace to clean up. 
llvm-svn: 152092
 2012-03-06 02:25:36 +00:00
Argyrios Kyrtzidis
c9658a580e Add include/llvm/ADT/UsuallyTinyPtrVector.h which is a vector that 
optimizes the case where there is only one element.

llvm-svn: 152090
 2012-03-06 02:08:48 +00:00
Evan Cheng
891cc85c9f Avoid finalizeBundles infinite looping. 
llvm-svn: 152089
 2012-03-06 02:00:52 +00:00
Owen Anderson
23d0deb35a Make it possible for a target to mark FSUB as Expand. This requires providing a default expansion (FADD+FNEG), and teaching DAGCombine not to form FSUBs post-legalize if they are not legal. 
llvm-svn: 152079
 2012-03-06 00:29:31 +00:00
Lang Hames
a49054ac9c Split fpscr into two registers: FPSCR and FPSCR_NZCV. 
The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.

llvm-svn: 152076
 2012-03-06 00:19:55 +00:00
Eli Friedman
eec5df7382 A few more cases of missing masking in ComputeMaskedBits; found by inspection. 
llvm-svn: 152070
 2012-03-05 23:22:40 +00:00
Jim Grosbach
91314c2db6 ARM vpush/vpop assembler mnemonics accept an optional size suffix. 
rdar://10988114

llvm-svn: 152068
 2012-03-05 23:16:31 +00:00
Jim Grosbach
b0d6469b77 Nuke a bit of dead code. 
llvm-svn: 152067
 2012-03-05 23:09:51 +00:00