1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-26 04:32:44 +01:00
Commit Graph

156241 Commits

Author SHA1 Message Date
Peter Collingbourne
b997552a11 Inline compareAddr function into its only caller. NFCI.
llvm-svn: 317045
2017-10-31 22:49:09 +00:00
Daniel Sanders
3f288c5370 Revert r317040: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC
The same bots fail but I believe I know what the issue is now. These bots are
missing the const_iterator versions of insert/emplace/etc. that were introduced
in C++11.

llvm-svn: 317042
2017-10-31 21:54:52 +00:00
Reid Kleckner
4dbf6ceb83 [codeview] Merge file checksum entries for DIFiles with the same absolute path
Change the map key from DIFile* to the absolute path string. Computing
the absolute path isn't expensive because we already have a map that
caches the full path keyed on DIFile*.

llvm-svn: 317041
2017-10-31 21:52:15 +00:00
Daniel Sanders
bb3be22102 Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC
Multi-instruction emission needs to ensure the the instructions are generated
a depth-first fashion. For example:
 (ADDWrr (SUBWrr a, b), c)
needs to emit the SUBWrr before the ADDWrr. However, our walk over
TreePatternNode's is highly context sensitive which makes it difficult to append
BuildMIActions in the order we want. To fix this, we now keep track of the
insertion point as we add actions. This will allow multi-insn emission to insert
BuildMI's in the correct place.

The previous commit failed on the Ubuntu bots using GCC 4.8. These bots didn't
like a call to emplace(). I've replaced it with insert() to see if it's a quirk
of the C++11 support.

llvm-svn: 317040
2017-10-31 21:34:53 +00:00
Marek Olsak
5cb35b4bac AMDGPU: Select s_buffer_load_dword with a non-constant SGPR offset
Summary:
Apps that benefit:
- alien isolation
- bioshock infinite
- civilization: beyond earth
- company of heroes 2
- dirt showdown
- dota 2
- F1 2015
- grid autosport
- hitman
- legend of grimrock
- serious sam 3: bfe
- shadow warrior
- talos principle
- total war: warhammer
- UE4 demos: effects cave, elemental, sun temple

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D38914

llvm-svn: 317038
2017-10-31 21:06:42 +00:00
Adrian Prantl
5bd9a961dd loop-rotate: simplify code by using llvm::findDbgValues(). (NFC)
llvm-svn: 317037
2017-10-31 21:03:22 +00:00
Daniel Sanders
fa8a5783fb Revert r317029: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC
The Linux bots don't seem to like this usage of emplace(). Reverting while I look into it.

llvm-svn: 317033
2017-10-31 20:29:28 +00:00
Benjamin Kramer
ec4a9b4088 Revert "[DWARF] Now that Optional is standard layout, put it into an union instead of splatting it."
GCC doesn't like it. This reverts commit r317028.

llvm-svn: 317030
2017-10-31 19:55:08 +00:00
Daniel Sanders
82ecab609d [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC
Multi-instruction emission needs to ensure the the instructions are generated
a depth-first fashion. For example:
  (ADDWrr (SUBWrr a, b), c)
needs to emit the SUBWrr before the ADDWrr. However, our walk over
TreePatternNode's is highly context sensitive which makes it difficult to append
BuildMIActions in the order we want. To fix this, we now keep track of the
insertion point as we add actions. This will allow multi-insn emission to insert
BuildMI's in the correct place.

llvm-svn: 317029
2017-10-31 19:54:05 +00:00
Benjamin Kramer
142ac789a5 [DWARF] Now that Optional is standard layout, put it into an union instead of splatting it.
No functionality change intended.

llvm-svn: 317028
2017-10-31 19:40:03 +00:00
Benjamin Kramer
81949eac53 [coro] Make Spill a proper struct instead of deriving from pair.
No functionality change.

llvm-svn: 317027
2017-10-31 19:22:55 +00:00
Daniel Sanders
b7f991b7ac [globalisel][tablegen] Factor out implicit def/use renderers from createAndImportInstructionRenderer(). NFC
Multi-instruction emission will require that we have separate handling for
the defs between the implicitly created temporaries and the rule outputs.
The former require new temporary vregs while the latter should copy existing
operands. Factor out the implicit def/use renderers to minimize the code
duplication when we implement that.

llvm-svn: 317025
2017-10-31 19:09:29 +00:00
Craig Topper
d491b73661 [SimplifyCFG] Use a more generic name for the selects created by SpeculativelyExecuteBB to prevent long names from being created
Currently the selects are created with the names of their inputs concatenated together. It's possible to get cases that chain these selects together resulting in long names due to multiple levels of concatenation. Our internal branch of llvm managed to generate names over 100000 characters in length on a particular test due to an extreme compounding of the names.

This patch changes the name to a generic name that is not dependent on its inputs.

Differential Revision: https://reviews.llvm.org/D39440

llvm-svn: 317024
2017-10-31 19:03:51 +00:00
Craig Topper
0b655fec9e [SimplifyCFG] Regenerate some test cases using update_test_checks.py to prepare for an upcoming commit. NFC
A future commit will change how some of the value names in the IR are generated which causes these tests to break in their current form. The script generates checks with regular expressions so it should be immune.

llvm-svn: 317023
2017-10-31 19:03:49 +00:00
Daniel Sanders
f99453aefd [globalisel][tablegen] Add infrastructure to potentially allow BuildMIAction to choose a mutatable instruction. NFC
Prepare for multiple instruction emission by allowing BuildMIAction to
search for a suitable matcher that will support mutation.

This patch deliberately neglects to add matchers aside from the root to
preserve NFC. That said, it should be noted that until we support mutations
other than just the opcode the chances of finding a non-root instruction
for which canMutate() is true, is essentially zero. Furthermore in the
presence of multi-instruction emission the chances of finding any
instruction for which canMutate() is true is also zero. Nevertheless, we
can't continue to require that all BuildMIAction's consider the root of the match
to be recyclable due to the risk of recycling it twice in the same rule.

llvm-svn: 317022
2017-10-31 18:50:24 +00:00
Simon Pilgrim
a834950f83 [X86][AVX512] Regenerate tests to remove retl/retq regex
These are only testing 64-bit targets so we don't need the regex

llvm-svn: 317021
2017-10-31 18:43:24 +00:00
Simon Pilgrim
9cb8b71cb7 [X86][AVX512] Split AVX512F and AVX512BW bool-vector bitcast tests
llvm-svn: 317020
2017-10-31 18:41:48 +00:00
Benjamin Kramer
f423bb4d8a [ADT] Split optional to only include copy mechanics and dtor for non-trivial types.
This makes uses of Optional more transparent to the compiler (and
clang-tidy) and generates slightly smaller code.

llvm-svn: 317019
2017-10-31 18:35:54 +00:00
Wolfgang Pieb
2c53dfefa1 [Metadata][NFC] Make MDNode::resolve() public in preparation for the fix to PR33930.
Reviewers: aprantl
llvm-svn: 317018
2017-10-31 18:25:28 +00:00
Daniel Sanders
24856518f6 [globalisel][tablegen] Allow any comment in DebugCommentAction. NFC
llvm-svn: 317017
2017-10-31 18:07:03 +00:00
Philip Reames
d06638559c [IndVarSimplify] Extract wrapper around SE-.isLoopInvariantPredicate [NFC]
This an intermediate state, the next patch will re-inline the markLoopInvariantPredicate function to reduce code duplication.

llvm-svn: 317016
2017-10-31 18:04:57 +00:00
Rui Ueyama
f0ff305346 [Support] Make the default chunk size of raw_fd_ostream to 1 GiB.
Previously, we call write(2) for each 32767 byte chunk. That is not
efficient because Linux can handle much larger write requests.
This patch changes the chunk size on Linux to 1 GiB.

This patch also changes the default chunks size to SSIZE_MAX. I think
that doesn't in practice change this function's behavior on any operating
system because SSIZE_MAX on 64-bit machine is unrealistically large,
and writing 2 GiB (SSIZE_MAX on 32-bit) on a 32-bit machine by a single
call of write(2) is also unrealistic, as the userspace is usually
limited to 2 GiB. That said, it is in general a good thing to do because
a write larger than SSIZE_MAX is implementation-defined in POSIX.

Differential Revision: https://reviews.llvm.org/D39444

llvm-svn: 317015
2017-10-31 17:37:20 +00:00
Philip Reames
e87a19c3aa [IndVarSimplify] Simplify code using a dictionary
Possibly very slightly slower, but this code is not performance critical and the readability benefit alone is huge.

llvm-svn: 317012
2017-10-31 17:06:32 +00:00
Reid Kleckner
6dce094074 [X86][AsmParser] Treat '%' as the modulo operator under Intel syntax
It can't be a register prefix, anyway. This is consistent with the masm
docs on MSDN: https://msdn.microsoft.com/en-us/library/t4ax90d2.aspx

This is a straight-forward extension of our support for "MOD"
implemented in https://reviews.llvm.org/D33876 / r306425

llvm-svn: 317011
2017-10-31 16:47:38 +00:00
Nico Weber
9406190dba LTOModule::isBitcodeFile() shouldn't assert when returning false.
Fixes a bunch of assert-on-invalid-bitcode regressions after 315483.
Expected<> calls assertIsChecked() in its dtor, and operator bool() only calls
setChecked() if there's no error. So for functions that don't return an error
itself, the Expected<> version needs explicit code to disarm the error that the
ErrorOr<> code didn't need.

https://reviews.llvm.org/D39437

llvm-svn: 317010
2017-10-31 16:39:47 +00:00
Reid Kleckner
c03d168784 [asan] Upgrade private linkage globals to internal linkage on COFF
COFF comdats require symbol table entries, which means the comdat leader
cannot have private linkage.

llvm-svn: 317009
2017-10-31 16:16:08 +00:00
Simon Pilgrim
b90b467bbf [X86][SSE] Add VSRLI/VSRAI/VSLLI demanded elts support to computeKnownBits/ComputeNumSignBits
Mainly a perf improvements as most combines will have occurred before we lower to these instructions

llvm-svn: 317005
2017-10-31 16:06:21 +00:00
Benjamin Kramer
d6177e6458 [LoopVectorize] Replace manual VPlan memory management with unique_ptr.
No functionality change intended.

llvm-svn: 317003
2017-10-31 14:58:22 +00:00
Jonas Devlieghere
30acec2960 [test] Fix dsymutil/cmdline.test
This fixes dsymutil/cmdline.test on platforms where the dsymutil binary
has an extension.

llvm-svn: 317001
2017-10-31 14:19:02 +00:00
Florian Hahn
4a7156f496 [Reassociate] Remove FIXME from looptest.ll (NFC)
Summary: The loop invariant add (i+j) is reassoicated, I think the FIXME can be removed, because this is what the test case tries to check (AFAIK). I also changed the test to use FileCheck.

Reviewers: mcrosier, davide

Reviewed By: mcrosier, davide

Subscribers: davide, llvm-commits

Differential Revision: https://reviews.llvm.org/D39424

llvm-svn: 317000
2017-10-31 14:06:31 +00:00
Jonas Devlieghere
17ac392c74 [dsymutil] Implement the --threads option
This patch adds the --threads option to dsymutil to process
architectures in parallel. The feature is already present in the version
distributed with Xcode, but was not yet upstreamed.

This is NFC as far as the linking behavior is concerned. As threads are
used automatically, the current tests cover the change in
implementation.

Differential revision: https://reviews.llvm.org/D39355

llvm-svn: 316999
2017-10-31 13:54:15 +00:00
Teresa Johnson
f1bd32e79d [ThinLTO] Double bits of module hash used for renaming
Summary:
Use 64 instead of 32 bits of the module hash as the suffix when renaming
after promotion to reduce the likelihood of a collision (which we
observed in a binary when using 32 bits).

Reviewers: pcc

Subscribers: llvm-commits, inglorion

Differential Revision: https://reviews.llvm.org/D39443

llvm-svn: 316996
2017-10-31 12:56:09 +00:00
Matthew Simpson
fa52fc8d71 [InstCombine] Simplify selects that test cmpxchg instructions
If a select instruction tests the returned flag of a cmpxchg instruction and
selects between the returned value of the cmpxchg instruction and its compare
operand, the result of the select will always be equal to its false value.

Differential Revision: https://reviews.llvm.org/D39383

llvm-svn: 316994
2017-10-31 12:34:02 +00:00
Ayman Musa
a556ca2ee3 Adding a shufflevector and select LLVM IR instructions fuzz tool
Based on similar python tool - utils/shuffle-fuzz.py - this tool extends the ability of it's previous by optionally attaching select instruction to the generated shufflevector instructions.
This was mainly developed to perform exhaustive testing of the X86 AVX512 masked shuffle instructions. But yet it can be used for various other targets.
The general design of the implementation is much modular than the original shuffle_fuzz.py tool, which makes it easier for anyone to extend it further.

Differential Revision: https://reviews.llvm.org/D38031

Change-Id: I0efc2aaa091b61a8a9552311c21cc77916a97111
llvm-svn: 316989
2017-10-31 11:39:31 +00:00
David Green
90105ec5c8 [LoopUnroll] Clean up remarks for unroll remainder
The optimisation remarks for loop unrolling with an unrolled remainder looks something like:

test.c:7:18: remark: completely unrolled loop with 3 iterations [-Rpass=loop-unroll]
            C[i] += A[i*N+j];
                 ^
test.c:6:9: remark: unrolled loop by a factor of 4 with run-time trip count [-Rpass=loop-unroll]
        for(int j = 0; j < N; j++)
        ^
This removes the first of the two messages.

Differential revision: https://reviews.llvm.org/D38725

llvm-svn: 316986
2017-10-31 10:47:46 +00:00
Michael Zuckerman
8e4ae49177 [AVX512] Adding new patterns for extract_subvector of vXi1
extract subvector of vXi1 from vYi1 is poorly supported by LLVM and most of the time end with an assertion.
This patch fixes this issue by adding new patterns to the TD file.

Reviewers:
1. guyblank
2. igorb
3. zvi
4. ayman
5. craig.topper

Differential Revision: https://reviews.llvm.org/D39292

Change-Id: Ideb4d7e946c8d40cfce2920891f2d89fe64c58f8
llvm-svn: 316981
2017-10-31 10:00:19 +00:00
Serguei Katkov
dad01a379f [CGP] Fix the detection of trivial case for addressing mode
The address can be presented as a bitcast of baseReg.
In this case it is still trivial but OriginalValue != baseReg.

llvm-svn: 316980
2017-10-31 07:01:35 +00:00
Max Kazantsev
0e30db695e [IRCE][NFC] Rename fields of InductiveRangeCheck
Rename `Offset`, `Scale`, `Length` into `Begin`, `Step`, `End` respectively
to make naming of similar entities for Ranges and Range Checks more
consistent.

Differential Revision: https://reviews.llvm.org/D39414

llvm-svn: 316979
2017-10-31 06:19:05 +00:00
Craig Topper
232eac1fb9 [X86] Make AVX512_512_SET0 XMM16-31 lower to 128-bit XOR when AVX512VL is enabled. Use 128-bit VLX instruction when VLX is enabled.
Unfortunately, this weakens our ability to do domain fixing when AVX512DQ is not enabled, but it is consistent with our 256-bit behavior.

Maybe we should add custom handling to domain fixing to allow EVEX integer XOR/AND/OR/ANDN to switch to VEX encoded fp instructions if the high registers aren't being used?

llvm-svn: 316978
2017-10-31 06:01:04 +00:00
Max Kazantsev
ffcc4669b7 [NFC] Get rid of variables used in assert only
llvm-svn: 316977
2017-10-31 05:33:58 +00:00
Philip Reames
eaa9b48ba6 [IndVarSimplify] Simplify code using preheader assumption
As noted in the nice block comment, the previous code didn't actually handle multi-entry loops correctly, it just assumed SCEV didn't analyze such loops.  Given SCEV has comments to the contrary, that seems a bit suspect.  More importantly, the pass actually requires loopsimplify form which ensures a loop-preheader is available.  Remove the excessive generaility and shorten the code greatly.

Note that we do successfully analyze many multi-entry loops, but we do so by converting them to single entry loops.  See the added test case.

llvm-svn: 316976
2017-10-31 05:16:46 +00:00
Max Kazantsev
568017d4d5 Reapply "[GVN] Prevent LoadPRE from hoisting across instructions that don't pass control flow to successors"
This patch fixes the miscompile that happens when PRE hoists loads across guards and
other instructions that don't always pass control flow to their successors. PRE is now prohibited
to hoist across such instructions because there is no guarantee that the load standing after such
instruction is still valid before such instruction. For example, a load from under a guard may be
invalid before the guard in the following case:
  int array[LEN];
  ...
  guard(0 <= index && index < LEN);
  use(array[index]);

Differential Revision: https://reviews.llvm.org/D37460

llvm-svn: 316975
2017-10-31 05:07:56 +00:00
Philip Reames
03929af30c [SimplifyIndVar] Extract out invariant expression handling
Previously, the code returned early from the *function* when it couldn't find a free expansion, it should be returning from the *transform*.  I don't have a test case, noticed this via inspection.

As a follow up, I'm going to revisit the logic in the extract function.  I think that essentially the whole helper routine can be replaced with SCEVExpander, but I wanted to do that in a series of separate commits.

llvm-svn: 316974
2017-10-31 04:19:06 +00:00
Craig Topper
2941e144f6 [X86] Clang-format some code. NFC
llvm-svn: 316973
2017-10-31 02:34:29 +00:00
Shoaib Meenai
b65a04dcd7 [cmake] Make check_linker_flags operate via linker flags
`check_linker_flags` currently sets the *compiler* flags (via
`CMAKE_REQUIRED_FLAGS`), and thus implicitly relies on cmake's default
behavior of passing the compiler flags to the linker. This breaks when
cmake's build rules have been altered to not pollute the link line with
compiler flags (which can be desirable for build cleanliness). Instead,
set `CMAKE_EXE_LINKER_FLAGS` explicitly and use `CMP0056` to ensure the
linker flags are passed along. Additionally, since we're inside a
function, we can just alter the variable directly (as the alteration
will be limited to the scope of the function) rather than saving and
restoring the old value.

Differential Revision: https://reviews.llvm.org/D39431

llvm-svn: 316972
2017-10-31 01:30:46 +00:00
Philip Reames
fa7b7b5937 Undo accidental commit
These files shouldn't have been submitted in 316967

llvm-svn: 316968
2017-10-31 00:04:09 +00:00
Philip Reames
96a93d11ec [CGP] Fix crash on i96 bit multiply
Issue found by llvm-isel-fuzzer on OSS fuzz, https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=3725

If anyone actually cares about > 64 bit arithmetic, there's a lot more to do in this area.  There's a bunch of obviously wrong code in the same function.  I don't have the time to fix all of them and am just using this to understand what the workflow for fixing fuzzer cases might look like.

llvm-svn: 316967
2017-10-30 23:59:51 +00:00
Simon Pilgrim
937b242735 Fix unused variable warnings. NFCI.
llvm-svn: 316964
2017-10-30 22:38:07 +00:00
Simon Pilgrim
21b08adda6 [SelectionDAG] Tidyup computeKnownBits extension/truncation cases. NFCI.
We don't need to extend/truncate the Known structure before calling computeKnownBits - it will reset at the start of the function.

llvm-svn: 316962
2017-10-30 22:23:57 +00:00
Javed Absar
9171bb47a2 [AArch64]: range loopify frame-lowering
llvm-svn: 316960
2017-10-30 22:00:06 +00:00