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Author SHA1 Message Date
Chris Lattner
b54e4baa26 add a missing break that caused a lot of failures last night :( 
llvm-svn: 25851
 2006-01-31 17:20:06 +00:00
Chris Lattner
b79e962b6b solaris won't clobber an existing symlink with ln -sf apparently 
llvm-svn: 25849
 2006-01-31 16:10:53 +00:00
Nate Begeman
7a83bb4285 Codegen 
bool %test(int %X) {
  %Y = seteq int %X, 13
  ret bool %Y
}

as

_test:
        addi r2, r3, -13
        cntlzw r2, r2
        srwi r3, r2, 5
        blr

rather than

_test:
        cmpwi cr7, r3, 13
        mfcr r2
        rlwinm r3, r2, 31, 31, 31
        blr

This has very little effect on most code, but speeds up analyzer 23% and
mason 11%

llvm-svn: 25848
 2006-01-31 08:17:29 +00:00
Chris Lattner
798747b798 okay, one more 
llvm-svn: 25847
 2006-01-31 07:45:45 +00:00
Chris Lattner
c831039792 another note 
llvm-svn: 25846
 2006-01-31 07:45:08 +00:00
Chris Lattner
5d718dbc1e More notes 
llvm-svn: 25845
 2006-01-31 07:43:33 +00:00
Chris Lattner
e0d5ccdecf another one 
llvm-svn: 25844
 2006-01-31 07:38:32 +00:00
Chris Lattner
66751830ed add a note 
llvm-svn: 25843
 2006-01-31 07:37:20 +00:00
Chris Lattner
1a0bf14366 add conditional moves of float and double values on int/fp condition codes. 
llvm-svn: 25842
 2006-01-31 07:26:55 +00:00
Chris Lattner
186b5f0887 example nate pointed out 
llvm-svn: 25841
 2006-01-31 07:16:34 +00:00
Chris Lattner
769e683663 treat conditional branches the same way as conditional moves (giving them 
an operand that contains the condcode), making things significantly simpler.

llvm-svn: 25840
 2006-01-31 06:56:30 +00:00
Chris Lattner
a999c688d5 compactify all of the integer conditional moves into one instruction that takes 
a CC as an operand.  Much smaller, much happier.

llvm-svn: 25839
 2006-01-31 06:49:09 +00:00
Chris Lattner
5aade7535c Add immediate forms of integer cmovs 
llvm-svn: 25838
 2006-01-31 06:24:29 +00:00
Chris Lattner
c1b80cb2fe Shrinkify 
llvm-svn: 25837
 2006-01-31 06:18:16 +00:00
Chris Lattner
8d9da62be7 implement test/Regression/TableGen/DagIntSubst.ll 
llvm-svn: 25836
 2006-01-31 06:02:35 +00:00
Chris Lattner
e6bed389d4 new testcase 
llvm-svn: 25835
 2006-01-31 06:01:40 +00:00
Chris Lattner
fcd00875a9 Add the full complement of conditional moves of integer registers. 
llvm-svn: 25834
 2006-01-31 05:26:36 +00:00
Chris Lattner
9d29548015 Compile this: 
void %X(int %A) {
        %C = setlt int %A, 123          ; <bool> [#uses=1]
        br bool %C, label %T, label %F

T:              ; preds = %0
        call int %main( int 0 )         ; <int>:0 [#uses=0]
        ret void

F:              ; preds = %0
        ret void
}

to this:

X:
        save -96, %o6, %o6
        subcc %i0, 122, %l0
        bg .LBBX_2      ! F
        nop
...

not this:

X:
        save -96, %o6, %o6
        sethi 0, %l0
        or %g0, 1, %l1
        subcc %i0, 122, %l2
        bg .LBBX_4      !
        nop
.LBBX_3:        !
        or %g0, %l0, %l1
.LBBX_4:        !
        subcc %l1, 0, %l0
        bne .LBBX_2     ! F
        nop

llvm-svn: 25833
 2006-01-31 05:05:52 +00:00
Chris Lattner
d33e8efd56 Only insert an AND when converting from BR_COND to BRCC if needed. 
llvm-svn: 25832
 2006-01-31 05:04:52 +00:00
Evan Cheng
49467b6b5b Added custom lowering of fabs 
llvm-svn: 25831
 2006-01-31 03:14:29 +00:00
Chris Lattner
830b1ad8cf add the 'lucas' optimization 
llvm-svn: 25830
 2006-01-31 02:55:28 +00:00
Chris Lattner
213a7b78fb I don't see why this optimization isn't safe, but it isn't, so disable it 
llvm-svn: 25829
 2006-01-31 02:45:52 +00:00
Chris Lattner
9b89cad951 Another high-prio selection performance bug 
llvm-svn: 25828
 2006-01-31 02:10:06 +00:00
Chris Lattner
e113238f5c Handle physreg input/outputs. We now compile this: 
int %test_cpuid(int %op) {
        %B = alloca int
        %C = alloca int
        %D = alloca int
        %A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
        %Bv = load int* %B
        %Cv = load int* %C
        %Dv = load int* %D
        %x = add int %A, %Bv
        %y = add int %x, %Cv
        %z = add int %y, %Dv
        ret int %z
}

to this:

_test_cpuid:
        sub %ESP, 16
        mov DWORD PTR [%ESP], %EBX
        mov %EAX, DWORD PTR [%ESP + 20]
        cpuid
        mov DWORD PTR [%ESP + 8], %ECX
        mov DWORD PTR [%ESP + 12], %EBX
        mov DWORD PTR [%ESP + 4], %EDX
        mov %ECX, DWORD PTR [%ESP + 12]
        add %EAX, %ECX
        mov %ECX, DWORD PTR [%ESP + 8]
        add %EAX, %ECX
        mov %ECX, DWORD PTR [%ESP + 4]
        add %EAX, %ECX
        mov %EBX, DWORD PTR [%ESP]
        add %ESP, 16
        ret

... note the proper register allocation.  :)

it is unclear to me why the loads aren't folded into the adds.

llvm-svn: 25827
 2006-01-31 02:03:41 +00:00
Chris Lattner
899754747c more mumbling 
llvm-svn: 25826
 2006-01-31 00:45:37 +00:00
Chris Lattner
76a85bd047 add some notes 
llvm-svn: 25825
 2006-01-31 00:20:38 +00:00
Evan Cheng
38aacb5f09 Don't generate complex sequence for SETOLE, SETOLT, SETULT, and SETUGT. Flip 
the order of the compare operands and generate SETOGT, SETOGE, SETUGE, and
SETULE instead.

llvm-svn: 25824
 2006-01-30 23:41:35 +00:00
Evan Cheng
7bcbf75f7f Don't generate (or setp, setae) for SETUGE. Simply flip the operands around and 
generate SETULT instead.

llvm-svn: 25823
 2006-01-30 23:39:40 +00:00
Chris Lattner
ce37ba3417 Print the most trivial inline asms. 
llvm-svn: 25822
 2006-01-30 23:00:08 +00:00
Chris Lattner
e24c6ef1f9 Fix a bug in my legalizer reworking that caused the X86 backend to not get 
a chance to custom legalize setcc, which broke a bunch of C++ Codes.
Testcase here: CodeGen/X86/2006-01-30-LongSetcc.ll

llvm-svn: 25821
 2006-01-30 22:43:50 +00:00
Chris Lattner
21fc565586 new testcase for the 'C++' failures last night. 
llvm-svn: 25820
 2006-01-30 22:43:10 +00:00
Chris Lattner
3ae06dac75 Fix FP constants, and the SparcV8/2006-01-22-BitConvertLegalize.ll failure from last night 
llvm-svn: 25819
 2006-01-30 22:20:49 +00:00
Evan Cheng
8ea651a9a4 i64 -> f32, f32 -> i64 and some clean up. 
llvm-svn: 25818
 2006-01-30 22:13:22 +00:00
Evan Cheng
d2d96373dc Always use FP stack instructions to perform i64 to f64 as well as f64 to i64 
conversions. SSE does not have instructions to handle these tasks.

llvm-svn: 25817
 2006-01-30 08:02:57 +00:00
Evan Cheng
153b75f154 One more getTargetNode() variant shouldn't hurt... 
llvm-svn: 25816
 2006-01-30 07:47:47 +00:00
Chris Lattner
baa47e9a6e Revamp the ICC/FCC reading instructions to be parameterized in terms of the 
SPARC condition codes, not in terms of the DAG condcodes.  This allows us to
write nice clean patterns for cmovs/branches.

llvm-svn: 25815
 2006-01-30 07:43:04 +00:00
Chris Lattner
7925da8b3b Compile: 
uint %test(uint %X) {
        %Y = call uint %llvm.ctpop.i32(uint %X)
        ret uint %Y
}

to:

test:
        save -96, %o6, %o6
        sll %i0, 0, %l0
        popc %l0, %i0
        restore %g0, %g0, %g0
        retl
        nop

instead of to 40 logical ops.  Note the shift-by-zero that clears the top
part of the 64-bit V9 register.

Testcase here: CodeGen/SparcV8/ctpop.ll

llvm-svn: 25814
 2006-01-30 06:14:02 +00:00
Chris Lattner
0551b3fcba new testcase 
llvm-svn: 25813
 2006-01-30 06:11:36 +00:00
Chris Lattner
5583b2e227 Clear the OpAction field before setting it. This allows a target to set 
an instruction operation action to Expand, then set it to Legal later.

llvm-svn: 25812
 2006-01-30 06:09:03 +00:00
Chris Lattner
0c7df7e9d1 If the target has V9 instructions, this pass is a noop, don't bother 
running it.

llvm-svn: 25811
 2006-01-30 05:51:14 +00:00
Chris Lattner
69658ab9a8 When in v9 mode, emit fabsd/fnegd/fmovd 
llvm-svn: 25810
 2006-01-30 05:48:37 +00:00
Chris Lattner
98667e5f6a First step towards V9 instructions in the V8 backend, two conditional move 
patterns.  This allows emission of this code:

t1:
        save -96, %o6, %o6
        subcc %i0, %i1, %l0
        move %icc, %i0, %i2
        or %g0, %i2, %i0
        restore %g0, %g0, %g0
        retl
        nop

instead of this:

t1:
        save -96, %o6, %o6
        subcc %i0, %i1, %l0
        be .LBBt1_2     !
        nop
.LBBt1_1:       !
        or %g0, %i2, %i0
.LBBt1_2:       !
        restore %g0, %g0, %g0
        retl
        nop

for this:

int %t1(int %a, int %b, int %c) {
        %tmp.2 = seteq int %a, %b
        %tmp3 = select bool %tmp.2, int %a, int %c
        ret int %tmp3
}

llvm-svn: 25809
 2006-01-30 05:35:57 +00:00
Chris Lattner
8b5958a832 Two changes: 
1. Default to having V9 instructions, instead of just V8.
2. unless -enable-sparc-v9-insts is passed, disable V9 (for use with llcbeta)

llvm-svn: 25807
 2006-01-30 04:57:43 +00:00
Chris Lattner
f0ea60bc01 When lowering SELECT_CC, see if the input is a lowered SETCC. If so, fold 
the two operations together.  This allows us to compile this:

void %two(int %a, int* %b) {
        %tmp.2 = seteq int %a, 0
        %tmp.0.0 = select bool %tmp.2, int 10, int 20
        store int %tmp.0.0, int* %b
        ret void
}

into:

two:
        save -96, %o6, %o6
        or %g0, 20, %l0
        or %g0, 10, %l1
        subcc %i0, 0, %l2
        be .LBBtwo_2    ! entry
        nop
.LBBtwo_1:      ! entry
        or %g0, %l0, %l1
.LBBtwo_2:      ! entry
        st %l1, [%i1]
        restore %g0, %g0, %g0
        retl
        nop

instead of:

two:
        save -96, %o6, %o6
        sethi 0, %l0
        or %g0, 1, %l1
        or %g0, 20, %l2
        or %g0, 10, %l3
        subcc %i0, 0, %l4
        be .LBBtwo_2    ! entry
        nop
.LBBtwo_1:      ! entry
        or %g0, %l0, %l1
.LBBtwo_2:      ! entry
        subcc %l1, 0, %l0
        bne .LBBtwo_4   ! entry
        nop
.LBBtwo_3:      ! entry
        or %g0, %l2, %l3
.LBBtwo_4:      ! entry
        st %l3, [%i1]
        restore %g0, %g0, %g0
        retl
        nop

llvm-svn: 25806
 2006-01-30 04:34:44 +00:00
Jeff Cohen
d80b0d7375 Add AddSymbol() method to DynamicLibrary to work around Windows limitation 
of being unable to search for symbols in an EXE.  It will also allow other
existing hacks to be improved.

llvm-svn: 25805
 2006-01-30 04:33:51 +00:00
Chris Lattner
4ba0e38a7a don't insert an and node if it isn't needed here, this can prevent folding 
of lowered target nodes.

llvm-svn: 25804
 2006-01-30 04:22:28 +00:00
Chris Lattner
a44182300b Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler. 
llvm-svn: 25803
 2006-01-30 04:09:27 +00:00
Chris Lattner
a1cc69e24e Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface, 
making isMaskedValueZeroForTargetNode simpler, and useable from other parts
of the compiler.

llvm-svn: 25802
 2006-01-30 04:08:18 +00:00
Jeff Cohen
adacd55e5d Add _CRT_SECURE_NO_DEPRECATE preprocessor symbol to make VS2005 happy. 
llvm-svn: 25801
 2006-01-30 04:07:08 +00:00
Chris Lattner
354340b1b1 Implement isMaskedValueZeroForTargetNode for the various v8 selectcc nodes, 
allowing redundant and's to be eliminated by the dag combiner.

llvm-svn: 25800
 2006-01-30 03:51:45 +00:00