Jim Grosbach
b6c76a2662
Add FIXME.
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llvm-svn: 117787
2010-10-30 14:54:23 +00:00
Jim Grosbach
951667ac39
Clean up comments.
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llvm-svn: 117785
2010-10-30 13:48:28 +00:00
Jim Grosbach
775afa274f
Tidy up.
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llvm-svn: 117782
2010-10-30 12:59:16 +00:00
Chris Lattner
45c679522d
stay out of the reserved namespace
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llvm-svn: 117773
2010-10-30 04:57:14 +00:00
Chris Lattner
deabc3d7fa
simplify this code.
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llvm-svn: 117771
2010-10-30 04:35:59 +00:00
Chris Lattner
3a36dd4a0b
split MaybeParseRegister into its two logical uses, eliminating malloc+free traffic.
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llvm-svn: 117769
2010-10-30 04:09:10 +00:00
Jim Grosbach
298cac8db3
Avoid re-evaluating MI.getNumOperands() every iteration of the loop.
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llvm-svn: 117766
2010-10-30 01:40:16 +00:00
Bob Wilson
183c466006
Overhaul memory barriers in the ARM backend. Radar 8601999.
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There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain. It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions. Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions. Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.
llvm-svn: 117756
2010-10-30 00:54:37 +00:00
Jim Grosbach
996d1280bd
Encode the register list operands for ARM mode LDM/STM instructions.
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llvm-svn: 117753
2010-10-30 00:37:59 +00:00
Bill Wendling
b68e0d0ee3
Some instructions end with an "ls" prefix, but it doesn't indicate that they are
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conditional. Check for those instructions explicitly.
llvm-svn: 117747
2010-10-29 23:50:21 +00:00
Jim Grosbach
9a473e23b8
Remove hard tab characters.
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llvm-svn: 117742
2010-10-29 23:23:15 +00:00
Jim Grosbach
7ca6ac347d
80 column fix.
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llvm-svn: 117741
2010-10-29 23:21:57 +00:00
Jim Grosbach
038d376c59
trailing whitespace
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llvm-svn: 117740
2010-10-29 23:21:03 +00:00
Jim Grosbach
7cf8dcc5bd
s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand
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encoder functions.
llvm-svn: 117738
2010-10-29 23:19:55 +00:00
Evan Cheng
7695213793
Fix fpscr <-> GPR latency info.
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llvm-svn: 117737
2010-10-29 23:16:55 +00:00
Jim Grosbach
e811e91d02
add FIXME
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llvm-svn: 117718
2010-10-29 21:56:51 +00:00
Jim Grosbach
fcfc42b7bb
Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it in
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the ARMExpandPseudos pass rather than during the asm lowering.
llvm-svn: 117714
2010-10-29 21:35:25 +00:00
Eric Christopher
bf7cf2a203
Handle comparison values we already have - this fixes the consumer-typeset
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failure for llvm-gcc on arm fast isel.
llvm-svn: 117710
2010-10-29 21:08:19 +00:00
Jim Grosbach
93fbda05ee
ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to
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handle it in the asm lowering.
llvm-svn: 117707
2010-10-29 20:37:06 +00:00
Jim Grosbach
52638aa1c8
Fix typo.
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llvm-svn: 117703
2010-10-29 20:21:49 +00:00
Jim Grosbach
4ca61d9877
ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS.
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llvm-svn: 117702
2010-10-29 20:21:36 +00:00
Jim Grosbach
162e3345fb
ARM mode LDREX*/STREX* binary encodings.
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llvm-svn: 117695
2010-10-29 19:58:57 +00:00
Jim Grosbach
5bc94b46a9
Encoding information for ARM conditional move instructions.
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llvm-svn: 117687
2010-10-29 19:28:17 +00:00
Evan Cheng
392d2cbdcc
Avoiding overly aggressive latency scheduling. If the two nodes share an
...
operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.
BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB
=>
BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB
This fixed the recent 256.bzip2 regression.
llvm-svn: 117675
2010-10-29 18:09:28 +00:00
Evan Cheng
92293993bd
- Don't schedule nodes with only MVT::Flag and MVT::Other values for latency.
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- Compute CopyToReg use operand latency correctly.
llvm-svn: 117674
2010-10-29 18:07:31 +00:00
Jim Grosbach
edec5cc6b8
Handle ARM addrmode5 instructions with an offset.
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llvm-svn: 117672
2010-10-29 17:41:25 +00:00
John Thompson
6115a7f1d4
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
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llvm-svn: 117667
2010-10-29 17:29:13 +00:00
Jim Grosbach
6f257bd31b
Revert 117660. Apparently it's not as trivial as that...
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llvm-svn: 117663
2010-10-29 16:50:53 +00:00
Jim Grosbach
8c9a2ee86e
ARM addrmode5 instructions have neither writeback nor post-indexed modes.
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llvm-svn: 117660
2010-10-29 16:38:59 +00:00
Jim Grosbach
29961ebfc5
Trailing whitespace.
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llvm-svn: 117651
2010-10-29 14:46:02 +00:00
Benjamin Kramer
f2442da5f6
ARMAsmParser: Plug a memory leak.
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llvm-svn: 117648
2010-10-29 09:43:39 +00:00
Eric Christopher
930a767468
Add an unreachable to silence warning - the switch is actually
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fully enumerated.
llvm-svn: 117647
2010-10-29 09:26:59 +00:00
Chris Lattner
115cd02d22
add simple support for addrmode5 operands, allowing
...
vldr.64 to work. I have no idea if this is fully right, but
it is in the right direction.
llvm-svn: 117626
2010-10-29 00:27:31 +00:00
Chris Lattner
ef237e6013
give better error diagnostics, for example:
...
t.s:1:14: error: invalid operand for instruction
vldr.64 d17, [r0]
^
instead of:
t.s:1:1: error: unrecognized instruction
vldr.64 d17, [r0]
^
llvm-svn: 117611
2010-10-28 21:41:58 +00:00
Chris Lattner
ba1e908431
hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes
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the opcode string in the inst dump, e.g.:
vmov r2, r3, d17 @ encoding: [0x31,0x2b,0x53,0xec]
@ <MCInst #989 VMOVRRD
@ <MCOperand Reg:68>
@ <MCOperand Reg:69>
@ <MCOperand Reg:19>
@ <MCOperand Imm:14>
@ <MCOperand Reg:0>>
The "VMOVRRD" is new.
llvm-svn: 117609
2010-10-28 21:37:33 +00:00
Chris Lattner
4210ffb9c5
move a method out of line.
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llvm-svn: 117605
2010-10-28 21:28:01 +00:00
Chris Lattner
b6c7a9e204
remove the rest of hte owningptr's, no functionality change.
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llvm-svn: 117603
2010-10-28 20:52:15 +00:00
Benjamin Kramer
fbfb8cf5f8
Reduce malloc thrashing.
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llvm-svn: 117572
2010-10-28 18:41:23 +00:00
Jim Grosbach
d02c1c7d77
PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.
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llvm-svn: 117571
2010-10-28 18:34:10 +00:00
Chris Lattner
0a21ad2553
rearrange ParseRegisterList.
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llvm-svn: 117560
2010-10-28 17:23:41 +00:00
Chris Lattner
a9c0f00f10
refactor some code to simplify it, eliminating some owningptr's.
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llvm-svn: 117559
2010-10-28 17:20:03 +00:00
Evan Cheng
bc4588c439
Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
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llvm-svn: 117531
2010-10-28 06:47:08 +00:00
Evan Cheng
fdc80a0316
Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh.
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llvm-svn: 117520
2010-10-28 02:00:25 +00:00
Evan Cheng
5c358e02ea
- Assign load / store with shifter op address modes the right itinerary classes.
...
- For now, loads of [r, r] addressing mode is the same as the
[r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
is "free".
llvm-svn: 117519
2010-10-28 01:49:06 +00:00
Dale Johannesen
b78530f9b0
Fix pastos in handling of AVX cvttsd2si, PR8491.
...
Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!
llvm-svn: 117514
2010-10-28 00:35:54 +00:00
Owen Anderson
e75f7c5419
Add correct NEON encodings for vtbl and vtbx.
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llvm-svn: 117513
2010-10-28 00:18:46 +00:00
Owen Anderson
008116cb71
Add correct NEON encodings for vext, vtrn, vuzp, and vzip.
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llvm-svn: 117512
2010-10-27 23:56:39 +00:00
Bob Wilson
2f8b69b196
Fix compiler warnings about signed/unsigned comparisons.
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llvm-svn: 117511
2010-10-27 23:49:00 +00:00
Evan Cheng
44d2802e1d
Shifter ops are not always free. Do not fold them (especially to form
...
complex load / store addressing mode) when they have higher cost and
when they have more than one use.
llvm-svn: 117509
2010-10-27 23:41:30 +00:00
Jim Grosbach
86ecfda983
Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
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the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752
llvm-svn: 117505
2010-10-27 23:12:14 +00:00