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15985 Commits

Author SHA1 Message Date
Owen Anderson
3a5f798790 Add tests for NEON encodings of vcge and vacge. 
llvm-svn: 117274
 2010-10-25 17:49:32 +00:00
Owen Anderson
757022131f Add a warning about our inability to test the encoding of vceq with immediate zero. 
llvm-svn: 117273
 2010-10-25 17:33:02 +00:00
Rafael Espindola
c6e7790c4b Add X86::reloc_global_offset_table and use it to have a single place where 
we check for _GLOBAL_OFFSET_TABLE_.

llvm-svn: 117241
 2010-10-24 17:35:42 +00:00
Eric Christopher
0dab5810aa Move rejection of NEON parameters earlier in fast isel call processing, 
note that we can actually handle some f64 arguments.

llvm-svn: 117209
 2010-10-23 09:37:17 +00:00
Benjamin Kramer
ed68a7877c Make the disassembler tables const so they end up in read-only memory. 
llvm-svn: 117206
 2010-10-23 09:10:44 +00:00
Michael J. Spencer
87c8212d41 X86: Emit _fltused instead of __fltused on Windows x64. 
llvm-svn: 117205
 2010-10-23 09:06:59 +00:00
Chandler Carruth
7dd652736f Move the remaining attribute macros to systematic names based on the attribute 
name and prefixed with 'LLVM_'.

llvm-svn: 117203
 2010-10-23 08:40:19 +00:00
Chandler Carruth
ea67aaa252 Remove a define which is never referenced. 
llvm-svn: 117202
 2010-10-23 08:25:16 +00:00
Chandler Carruth
7799a873bb Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names 
until other LLVM projects using these are cleaned up.

llvm-svn: 117200
 2010-10-23 08:10:43 +00:00
Evan Cheng
71b2f935db Enable ARM fastcc. 
llvm-svn: 117194
 2010-10-23 02:19:37 +00:00
Evan Cheng
132906a2d3 Latency between CPSR def and branch is zero. 
llvm-svn: 117192
 2010-10-23 02:04:38 +00:00
Jim Grosbach
6d65ad0408 Trailing whitespace. 
llvm-svn: 117188
 2010-10-22 23:48:29 +00:00
Gabor Greif
6e58dbc9e4 fix memory-layout assumption which only holds on little-endian systems 
llvm-svn: 117176
 2010-10-22 23:16:11 +00:00
Jim Grosbach
bba77cca02 ARM mode encoding information for CLZ, RBIT, REV*, and PKH*. 
llvm-svn: 117165
 2010-10-22 22:12:16 +00:00
Evan Cheng
20b70697bb Transfer implicit ops when forming load multiple and return instructions. 
llvm-svn: 117151
 2010-10-22 21:29:58 +00:00
Owen Anderson
424434414e Add correct NEON encodings for vqdmlal. 
llvm-svn: 117134
 2010-10-22 19:35:48 +00:00
Jim Grosbach
10195e9b73 Add the encoding information for the rest of the ARM mode multiply instructions. 
llvm-svn: 117133
 2010-10-22 19:15:30 +00:00
Owen Anderson
2bbdc62e17 Provide correct encodings for NEON vmlal. 
llvm-svn: 117131
 2010-10-22 19:05:25 +00:00
Evan Cheng
e5b7a3a09f Silence compiler warnings. 
llvm-svn: 117128
 2010-10-22 18:57:05 +00:00
Owen Anderson
ada2b33321 Provide correct NEON encodings for vmla. 
llvm-svn: 117126
 2010-10-22 18:54:37 +00:00
Jim Grosbach
ca2897a0ca More ARM multiply instuction binary encodings. 
llvm-svn: 117121
 2010-10-22 18:35:16 +00:00
Evan Cheng
efac5b5f8d Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by -arm-fastcc for now. 
llvm-svn: 117119
 2010-10-22 18:23:05 +00:00
Jim Grosbach
eabb7c5bd1 Parameterize a bit of ARM encoding information, simplifying some instruction 
definitions.

llvm-svn: 117114
 2010-10-22 17:42:06 +00:00
Benjamin Kramer
9e988fe81e Make some symbols static, move classes into anonymous namespaces. 
llvm-svn: 117111
 2010-10-22 17:35:07 +00:00
Jim Grosbach
0ae6bf8095 More ARM multiply instruction encoding information. 
llvm-svn: 117108
 2010-10-22 17:16:17 +00:00
Wesley Peck
488027efa3 Making the e_machine configurable by the target backend in ELFObjectWriter. 
llvm-svn: 117099
 2010-10-22 15:52:49 +00:00
Andrew Trick
b9e8700beb Reverting r117031 to cleanup valgrind errors. 
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.

llvm-svn: 117087
 2010-10-22 03:58:29 +00:00
Eric Christopher
58a6e62c08 Add some basic ret instruction support to arm fast-isel. 
llvm-svn: 117085
 2010-10-22 01:28:00 +00:00
Sean Callanan
9a40554de4 Fixed handling of immediate operand sizes, which 
weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix.  Also added
a test case for this.

llvm-svn: 117084
 2010-10-22 01:24:11 +00:00
Jim Grosbach
d86073aa9a ARM binary encoding for some of the multiply instructions. 
llvm-svn: 117080
 2010-10-21 22:52:30 +00:00
Jim Grosbach
7c42142b71 ARM binary encodings for MVN variants. 
llvm-svn: 117076
 2010-10-21 22:19:32 +00:00
Jim Grosbach
cb41e97b5c ARM Binary encoding information for BFC/BFI instructions. 
llvm-svn: 117072
 2010-10-21 22:03:21 +00:00
Eric Christopher
59683c9d71 These don't need to be virtual. 
llvm-svn: 117068
 2010-10-21 21:47:51 +00:00
Owen Anderson
f84632744e Move the encoding logic for Q registers into getMachineOpValue(). 
llvm-svn: 117060
 2010-10-21 20:49:13 +00:00
Owen Anderson
ba2ac80921 ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower 
half of the Q register), rather than with just regno.  This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.

llvm-svn: 117056
 2010-10-21 20:21:49 +00:00
Eric Christopher
7ded7e88c8 Handle storing args to the stack for calls. 
llvm-svn: 117055
 2010-10-21 20:09:54 +00:00
Wesley Peck
8a77999240 Adding initial AsmParser implementation for the MBlaze backend. It is 
mostly based on the ARM AsmParser at this time and is not particularly
functional.

Changed the MBlaze data layout from:
    "E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32"
to:
    "E-p:32:32:32-i8:8:8-i16:16:16"
because the MicroBlaze doesn't have i64, f64, v64, or v128 data types.

Cleaned up the MBlaze source code:
    1. The floating point register class has been removed. The
       MicroBlaze does not have floating point registers. Floating
       point values are simply stored in integer registers.
    2. Renaming the CPURegs register class to GPR to reflect the
       standard naming.
    3. Removing a lot of stale code from AsmPrinter after
       the conversion to InstPrinter.
    4. Simplified sign extended loads by marking them as
       expanded in ISelLowering.

llvm-svn: 117054
 2010-10-21 19:48:38 +00:00
Eric Christopher
b15029ea7e More load/store refactoring, call reg+offset simplification from within 
the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.

llvm-svn: 117051
 2010-10-21 19:40:30 +00:00
Jim Grosbach
f35d3b2aa1 trailing whitespace 
llvm-svn: 117050
 2010-10-21 19:38:40 +00:00
Owen Anderson
51a6bc3b27 Add correct NEON encodings for vhadd and vrhadd. 
llvm-svn: 117047
 2010-10-21 18:55:04 +00:00
Owen Anderson
dce283c7db Add correct encodings for NEON vaddw.s* and vaddw.u*. 
llvm-svn: 117040
 2010-10-21 18:20:25 +00:00
Owen Anderson
7d90c72edf Provide correct NEON encodings for vaddl.u* and vaddl.s*. 
llvm-svn: 117039
 2010-10-21 18:09:17 +00:00
Kevin Enderby
c63105a064 More tweaks to X86 instructions to allow the 'w' suffix in places it makes 
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler allows
for these instructions.  Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).

llvm-svn: 117031
 2010-10-21 17:16:46 +00:00
Duncan Sands
b458f1dc85 The return value of this call is not used, so no point 
in assigning it to a variable (gcc-4.6 warning).

llvm-svn: 117024
 2010-10-21 16:06:28 +00:00
Duncan Sands
0c166168a0 Remove some variables that are never really used 
(gcc-4.6 warns about these).

llvm-svn: 117021
 2010-10-21 16:03:28 +00:00
Duncan Sands
8c5f243aa0 Add parentheses to pacify gcc, which warns otherwise. 
llvm-svn: 117020
 2010-10-21 16:02:12 +00:00
Wesley Peck
b100615cc6 Removing stale AsmPrinter directory from MicroBlaze backend. 
llvm-svn: 116998
 2010-10-21 05:05:06 +00:00
Oscar Fuentes
00ad8b9b29 Deleted lib/Target/MBlaze/AsmPrinter/CMakeLists.txt. This way the 
CMake build does not try to build that library, which collides with
MBlaze/InstPrinter.

llvm-svn: 116997
 2010-10-21 05:01:26 +00:00
Wesley Peck
d646a12f25 Recommit 116986 with capitalization typo fixed. 
llvm-svn: 116993
 2010-10-21 03:57:26 +00:00
Andrew Trick
4a3b819c1f putback r116983 and fix simple-fp-encoding.ll tests 
llvm-svn: 116992
 2010-10-21 03:40:16 +00:00
Wesley Peck
3478e641b9 Reverting the commit 116986. It was breaking the build on llvm-x86_64-linux though it 
compiles on OS X. I'll ensure that it builds on a linux machine before committing
again.

llvm-svn: 116991
 2010-10-21 03:34:22 +00:00
Owen Anderson
7da515c665 Revert r116983, which is breaking all the buildbots. 
llvm-svn: 116987
 2010-10-21 03:11:16 +00:00
Wesley Peck
c50372298d Major update of the MicroBlaze backend. The new features are: 
1. A delay slot filler that searches for valid instructions
       to fill the delay slot with. Previously NOPs would always
       be inserted into delay slots.
    2. Support for MC based instruction printer added.
    3. Support for MC based machine code generation and ELF
       file generation. ELF file generation does not yet
       completely work as much of the ELF support infrastructure
       is still x86/x86-64 specific.
    4. General clean up of the MBlaze backend code. Much of the
       tablegen code has been cleanup and simplified.

Bug Fixes:
    1. Removed duplicate periods from subtarget feature descriptions.
    2. Many of the instructions had bad machine code information
       in the tablegen files. Much of this has been fixed.

llvm-svn: 116986
 2010-10-21 03:09:55 +00:00
Michael J. Spencer
5a68d7ce94 X86: Add alloca probing to dynamic alloca on Windows. Fixes PR8424. 
llvm-svn: 116984
 2010-10-21 01:41:01 +00:00
Evan Cheng
0b9eaaf45d Add missing scheduling itineraries for transfers between core registers and VFP registers. 
llvm-svn: 116983
 2010-10-21 01:12:00 +00:00
Owen Anderson
a685f8e90a Implement correct encodings for NEON vadd, both integer and floating point. 
llvm-svn: 116981
 2010-10-21 00:48:00 +00:00
Michael J. Spencer
b9cffadc06 CodeGen-Windows: Only emit _fltused if a VarArg function is called with floating point args. 
This should be the minimum set of functions that could possibly need it.

llvm-svn: 116978
 2010-10-21 00:08:21 +00:00
Eric Christopher
7989939d87 Custom lower f64 args passed in integer registers. 
llvm-svn: 116977
 2010-10-21 00:01:47 +00:00
Michael J. Spencer
54b462089f Fix Whitespace. 
llvm-svn: 116972
 2010-10-20 23:40:27 +00:00
Bill Wendling
c7ef66fcf2 Add encoding for moving a value between two ARM core registers and a doublework 
extension register.

llvm-svn: 116970
 2010-10-20 23:37:40 +00:00
Bill Wendling
0f96ff63b3 Add encodings for movement between ARM core registers and single-precision 
registers.

llvm-svn: 116961
 2010-10-20 22:44:54 +00:00
Dale Johannesen
a324c8c6bd Fix crash introduced in 116852. 8573915. 
llvm-svn: 116955
 2010-10-20 22:03:37 +00:00
Dale Johannesen
58fe3193a6 Remove Synthesizable from the Type system; as MMX vector 
types are no longer Legal on X86, we don't need it.
No functional change.  8499854.

llvm-svn: 116947
 2010-10-20 21:32:10 +00:00
Rafael Espindola
0a50bbaee1 Handle _GLOBAL_OFFSET_TABLE_ correctly. 
llvm-svn: 116932
 2010-10-20 16:46:08 +00:00
Chandler Carruth
55850cad48 Remove remaining uses of ATTRIBUTE_UNUSED on variables, and delete three 
#includes in the process.

llvm-svn: 116919
 2010-10-20 08:27:02 +00:00
Eric Christopher
78c7e84ce5 Fix a TODO by removing some unnecesary copies. 
llvm-svn: 116915
 2010-10-20 08:02:24 +00:00
Jim Grosbach
ebb4bc2c05 Fix backwards conditional. 
llvm-svn: 116897
 2010-10-20 01:10:01 +00:00
Jim Grosbach
c77e19ac99 Add dynamic realignment when rematerializing the base register. 
llvm-svn: 116886
 2010-10-20 00:02:50 +00:00
Jim Grosbach
5f33ecfc98 Nuke a commented out bit that got missed a while back. 
llvm-svn: 116883
 2010-10-19 23:48:47 +00:00
Jim Grosbach
a8c0be5343 Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any 
setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268

llvm-svn: 116879
 2010-10-19 23:27:08 +00:00
Jim Grosbach
d7916d7468 Update comments to remove obsolete references. 
llvm-svn: 116863
 2010-10-19 21:34:47 +00:00
Dale Johannesen
ee87cbe4e9 Enable using vdup for vector constants which are splat of 
integers by default, and remove the controlling flag, now
that LICM will hoist such vdup's.  8003375.

llvm-svn: 116852
 2010-10-19 20:00:17 +00:00
Evan Cheng
1c8dafd12a Re-enable register pressure aware machine licm with fixes. Hoist() may have 
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.

llvm-svn: 116845
 2010-10-19 18:58:51 +00:00
Owen Anderson
46990c17f7 Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which 
must be called in the pass's constructor.  This function uses static dependency declarations to recursively initialize
the pass's dependencies.

Clients that only create passes through the createFooPass() APIs will require no changes.  Clients that want to use the
CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h
before parsing commandline arguments.

I have tested this with all standard configurations of clang and llvm-gcc on Darwin.  It is possible that there are problems
with the static dependencies that will only be visible with non-standard options.  If you encounter any crash in pass
registration/creation, please send the testcase to me directly.

llvm-svn: 116820
 2010-10-19 17:21:58 +00:00
Daniel Dunbar
6ff550c84d Revert r116781 "- Add a hook for target to determine whether an instruction def 
is", which breaks some nightly tests.

llvm-svn: 116816
 2010-10-19 17:14:24 +00:00
Che-Liang Chiou
bc4f00f42d Add lower argument and return of device function 
llvm-svn: 116805
 2010-10-19 13:14:40 +00:00
Michael J. Spencer
e528f2588f X86: Add MS-CRT libcalls. 
llvm-svn: 116801
 2010-10-19 07:32:52 +00:00
Michael J. Spencer
cd6be63d05 Fix Whitespace. 
llvm-svn: 116800
 2010-10-19 07:32:42 +00:00
Evan Cheng
9c3f6f486e - Add a hook for target to determine whether an instruction def is 
"long latency" enough to hoist even if it may increase spilling. Reloading
  a value from spill slot is often cheaper than performing an expensive
  computation in the loop. For X86, that means machine LICM will hoist
  SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
  instructions.
- Enable register pressure aware machine LICM by default.

llvm-svn: 116781
 2010-10-19 00:55:07 +00:00
Bob Wilson
c3fb4427f4 Support alignment for NEON vld-lane and vst-lane instructions. 
llvm-svn: 116776
 2010-10-19 00:16:32 +00:00
Kevin Enderby
8a3030c6af Added a few tweaks to the Intel Descriptor-table support instructions to allow 
word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes.  This is again for use just with assembly source for llvm-mc .

llvm-svn: 116773
 2010-10-19 00:01:44 +00:00
Jim Grosbach
10fd33ecfc ARM encoding information for [SU]SAT* instructions. 
llvm-svn: 116768
 2010-10-18 23:35:38 +00:00
Eric Christopher
5850afe5f2 Revert r116220 - thus turning arm fast isel back on by default. 
llvm-svn: 116762
 2010-10-18 22:53:53 +00:00
Bill Wendling
3b3d9aaa86 Don't recompute MachineRegisterInfo in the Optimize* method. 
llvm-svn: 116750
 2010-10-18 21:22:31 +00:00
Jim Grosbach
ffb06eda57 For Thumb2, try to use frame pointer references for stack slots even when a 
base register is available. rdar://8525298

llvm-svn: 116729
 2010-10-18 18:39:46 +00:00
Rafael Espindola
7cc236c87f Produce ELF::R_386_GOTPC relocations. 
llvm-svn: 116728
 2010-10-18 18:36:12 +00:00
Kevin Enderby
cb18d38b76 Added a handful of x86-32 instructions that were missing so that llvm-mc would 
be more complete.  These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files.  Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added.  Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records.  More missing instructions will be coming.

llvm-svn: 116716
 2010-10-18 17:04:36 +00:00
Jim Grosbach
3e41568604 ARM addrmode4 instructions (ldm, stm and friends) can't encode an immediate 
offset for stack references. Make sure we take that into account when
deciding whether to reserver an emergency spill slot for the register
scavenger. rdar://8559625

llvm-svn: 116714
 2010-10-18 16:48:59 +00:00
Jim Grosbach
f93e92a4c1 Grammar tweak. 
llvm-svn: 116712
 2010-10-18 16:38:50 +00:00
Kalle Raiskila
3cdfdd9383 Improve lowering of sext to i128 on SPU. 
The old algorithm inserted a 'rotqmbyi' instruction which was
both redundant and wrong - it made shufb select bytes from the
wrong end of the input quad.

llvm-svn: 116701
 2010-10-18 09:34:19 +00:00
Eric Christopher
e453bd6697 Remove the check for invalid calling conventions. Testing shows that they're 
working just fine.

llvm-svn: 116698
 2010-10-18 06:49:12 +00:00
Eric Christopher
6287738105 Lift arg promotion from the X86 backend. This should be unified at some point. 
llvm-svn: 116694
 2010-10-18 02:17:53 +00:00
Eric Christopher
79c2206640 Now that we handle all allocas via a non-SP reg offset remove all of the 
special case handling for ARM::SP.

llvm-svn: 116688
 2010-10-17 11:08:44 +00:00
Eric Christopher
d99f79f92b Allow more load types to be materialized through the allocas. 
llvm-svn: 116683
 2010-10-17 06:07:26 +00:00
Eric Christopher
5fcaab5d0e Optimize GEP off of intermediate allocas. 
llvm-svn: 116681
 2010-10-17 01:51:42 +00:00
Eric Christopher
20bbcbeceb Fix comment. 
llvm-svn: 116680
 2010-10-17 01:42:53 +00:00
Eric Christopher
d9b4b47b9a Turn on AddOperator folding in GEP. 
llvm-svn: 116679
 2010-10-17 01:41:46 +00:00
Eric Christopher
490f82bc32 Use the i12 immediate versions of the load instructions - they're handled 
more in the post-passes.

llvm-svn: 116678
 2010-10-17 01:40:27 +00:00
Rafael Espindola
be5c52d2dc Add a MCObjectFormat class so that code common to all targets that use a 
single object format can be shared.

This also adds support for

mov zed+(bar-foo), %eax

on ELF and COFF targets.

llvm-svn: 116675
 2010-10-16 18:23:53 +00:00
Michael J. Spencer
e57b670425 X86-Windows: Emit an undefined global __fltused symbol when targeting Windows 
if any floating point arguments are passed to an external function.

llvm-svn: 116665
 2010-10-16 08:25:41 +00:00
Eric Christopher
98c6ce755a Fix some funky formatting that got through. 
llvm-svn: 116653
 2010-10-16 01:10:35 +00:00
Bill Wendling
8e4ceb45f2 ARMCodeEmitter::emitMiscInstruction is dead. Long live 
ARMCodeEmitter::emitMiscInstruction!

llvm-svn: 116644
 2010-10-15 23:35:12 +00:00
Eric Christopher
69eaf30a42 Make sure offset is 0 for load/store register to the stack call. 
llvm-svn: 116640
 2010-10-15 23:07:10 +00:00
Eric Christopher
c6e4aaec0a Formatting. 
llvm-svn: 116635
 2010-10-15 22:49:28 +00:00
Eric Christopher
7f8c3dff07 Fix else if -> if in store machinery. 
llvm-svn: 116628
 2010-10-15 22:32:37 +00:00
Bill Wendling
64d2bf006c Reformatting. No functionalogicality changes. 
llvm-svn: 116625
 2010-10-15 21:50:45 +00:00
Eric Christopher
a875589580 Refactor ARM fast-isel reg + offset to be a base + offset. 
llvm-svn: 116622
 2010-10-15 21:32:12 +00:00
Jim Grosbach
5d7a5f8d33 Encoding information for the various ARM saturating add/sub instructions. 
llvm-svn: 116612
 2010-10-15 19:49:46 +00:00
Jim Grosbach
785858b2ba ARM binary encoding information for RSB and RSC instructions. 
llvm-svn: 116604
 2010-10-15 18:42:41 +00:00
Jim Grosbach
440b0e6b34 Don't mark argument value stores as immutable, as otherwise the post-RA 
scheduler may reorder loads from them before the stores and other such
badness. PR8347. Patch by David Meyer

llvm-svn: 116602
 2010-10-15 18:34:47 +00:00
Bob Wilson
3b63270ed3 Use simple RegState::Define flag instead of getDefRegState(true). 
llvm-svn: 116601
 2010-10-15 18:25:59 +00:00
Eric Christopher
b287ab82d7 Expand GEP handling for constant offsets. 
llvm-svn: 116594
 2010-10-15 18:02:07 +00:00
Jim Grosbach
cb52aee60e When expanding the MOVsr[la]_flag pseudos, the CPSR implicit def becomes 
an explicit def. Make sure to capture that properly. rdar://8556556

llvm-svn: 116591
 2010-10-15 17:35:17 +00:00
Jim Grosbach
67f94c42d8 ARM mode encoding information for UBFX and SBFX instructions. 
llvm-svn: 116588
 2010-10-15 17:15:16 +00:00
Bob Wilson
6b6b53ad6f Remove unused ARMISD::AND selection DAG node. 
llvm-svn: 116566
 2010-10-15 04:34:40 +00:00
Bob Wilson
fcc42f2f3a ARM instructions that are both predicated and set the condition codes 
have been printed with the "S" modifier after the predicate.  With ARM's
unified syntax, they are supposed to go in the other order.  We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM.  Apparently we don't generate these instructions often because no one
noticed until now.  Thanks to Bill Wendling for the testcase!

llvm-svn: 116563
 2010-10-15 03:23:44 +00:00
Jim Grosbach
b01bcbd047 Encoding info for extension instructions. 
llvm-svn: 116560
 2010-10-15 02:29:58 +00:00
Jim Grosbach
6da1b52d7b Add missing Rd encoding for MOVs instruction. 
llvm-svn: 116537
 2010-10-14 23:28:31 +00:00
Jim Grosbach
804505c7d4 Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos 
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.

llvm-svn: 116534
 2010-10-14 22:57:13 +00:00
Jim Grosbach
29dc23398f Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx' 
pseudonym.

llvm-svn: 116512
 2010-10-14 20:43:44 +00:00
Jim Grosbach
73c78f8790 MOVi16 and MOVT ARM mode encodings. 
llvm-svn: 116498
 2010-10-14 18:54:27 +00:00
Jim Grosbach
6d5cb39757 Simplify encoding information and add 'dst' operand info for TAILJMP. 
llvm-svn: 116488
 2010-10-14 17:24:28 +00:00
Oscar Fuentes
1f9f1cc125 Remove explicit dependency of LLVMARMCodeGen on LLVMARMAsmPrinter. It 
creates a cyclic dependency that breaks the build when
BUILD_SHARED_LIBS=ON

llvm-svn: 116480
 2010-10-14 15:54:46 +00:00
Eric Christopher
9060ac1be3 Handle more complex GEP based loads and add a few TODOs to deal with 
GEP + alloca.

llvm-svn: 116474
 2010-10-14 09:29:41 +00:00
Bill Wendling
2c335d364c Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on 
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.

llvm-svn: 116471
 2010-10-14 02:33:26 +00:00
Bill Wendling
33a2ecd5e4 Add encoding for 'fmstat'. 
llvm-svn: 116466
 2010-10-14 01:19:34 +00:00
Bill Wendling
cd41f22ec1 - Add encodings for multiply add/subtract instructions in all their glory. 
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.

llvm-svn: 116464
 2010-10-14 01:02:08 +00:00
Jim Grosbach
684289bc3c Regenerate. No functional change, just cleanup. 
llvm-svn: 116459
 2010-10-14 00:15:18 +00:00
Jim Grosbach
151502662e Detabify and clean up 80 column violations. 
llvm-svn: 116454
 2010-10-13 23:47:11 +00:00
Jim Grosbach
506b966b9d A few 80 column fixes. 
llvm-svn: 116451
 2010-10-13 23:34:31 +00:00
Jim Grosbach
2e8a589fb2 trailing whitespace 
llvm-svn: 116450
 2010-10-13 23:12:26 +00:00
Jim Grosbach
41cd0dd4ba Add a FIXME. 
llvm-svn: 116449
 2010-10-13 22:55:33 +00:00
Jim Grosbach
4c80dbda49 Add operand encoding bits for SMC and SVC in ARM mode. 
llvm-svn: 116447
 2010-10-13 22:38:23 +00:00
Jim Grosbach
66822f70b8 More encoding cleanup. Also add register Rd operands for indirect branches. 
llvm-svn: 116444
 2010-10-13 22:09:34 +00:00
Jim Grosbach
630efeb050 Simplify some ARM encoding information. 
llvm-svn: 116440
 2010-10-13 21:48:54 +00:00
Eric Christopher
19be5bd87c Update comment. 
llvm-svn: 116438
 2010-10-13 21:41:51 +00:00
Jim Grosbach
f1d59d0fd5 Add a FIXME. The ADR instruction is a bit odd. 
llvm-svn: 116437
 2010-10-13 21:32:30 +00:00
Jim Grosbach
1699d40f80 Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern 
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

llvm-svn: 116432
 2010-10-13 21:00:04 +00:00
Bill Wendling
bf63d6eb63 Add MC encodings for VCVT* instrunctions. 
llvm-svn: 116431
 2010-10-13 20:58:46 +00:00
Jim Grosbach
3a4bfe4573 Add a FIXME. 
llvm-svn: 116428
 2010-10-13 20:38:04 +00:00
Jim Grosbach
d079fee8b1 Make a few more bits of some simple instructions explicit. nop, yield, wfe, 
wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.

llvm-svn: 116427
 2010-10-13 20:30:55 +00:00
Jim Grosbach
8f0bea85bf Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions. 
llvm-svn: 116421
 2010-10-13 19:56:10 +00:00
Jim Grosbach
79156dadf2 Fix encoding for compares. No Rd register. 
llvm-svn: 116414
 2010-10-13 18:05:25 +00:00
Jim Grosbach
9c4a598ef2 Add ARM mode operand encoding information for ADDE/SUBE instructions. 
llvm-svn: 116412
 2010-10-13 18:00:52 +00:00
Rafael Espindola
b1ae74bd73 Fix another case where we were preferring instructions with large 
immediates instead of 8 bits ones.

llvm-svn: 116410
 2010-10-13 17:14:25 +00:00
Rafael Espindola
ff7f11c151 Fix PR8365 by adding a more specialized Pat that checks if an 'and' with 
8 bit constants can be used.

llvm-svn: 116403
 2010-10-13 13:31:20 +00:00
Eric Christopher
f7ab2cd3df Start handling more global variables. 
llvm-svn: 116401
 2010-10-13 09:11:46 +00:00
Evan Cheng
d07bee932d Limit load / store issues (at least until we have a true multi-issue aware scheduler). 
llvm-svn: 116389
 2010-10-13 01:54:21 +00:00
Bill Wendling
6d8a23c978 Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test 
just yet.

llvm-svn: 116386
 2010-10-13 01:17:33 +00:00
Bill Wendling
ea062d454d Add encodings for VCVT instructions. 
llvm-svn: 116385
 2010-10-13 00:56:35 +00:00