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Commit Graph

14 Commits

Author SHA1 Message Date
David Greene
b149019c5d [AVX] Constify Inits
Make references to Inits const everywhere.  This is the final step
before making them unique.

llvm-svn: 136485
2011-07-29 19:07:05 +00:00
Owen Anderson
b651954088 Third time's the charm for implementing tied operand decoding properly.
llvm-svn: 136478
2011-07-29 18:28:52 +00:00
Owen Anderson
b905884f67 Fix a case where, when trying to track tied operands, we'd accidentally overwrite our mapping.
llvm-svn: 136467
2011-07-29 17:32:03 +00:00
Owen Anderson
8e67a44e7c Enhance the fixed-length decoder emitter to support tied operands.
llvm-svn: 136431
2011-07-28 23:56:20 +00:00
Owen Anderson
3650feb7f7 Enhance the fixed-length decoder emitter to support parsing scattered fields.
llvm-svn: 136405
2011-07-28 21:54:31 +00:00
Owen Anderson
ad0f17c102 Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM.
llvm-svn: 135524
2011-07-19 21:06:00 +00:00
Eric Christopher
3dd1f02420 Revert r134921, 134917, 134908 and 134907. They're causing failures
in multiple buildbots.

llvm-svn: 134936
2011-07-11 23:06:52 +00:00
David Greene
096bf5c02b [AVX] Make Inits Foldable
Manage Inits in a FoldingSet.  This provides several benefits:

- Memory for Inits is properly managed

- Duplicate Inits are folded into Flyweights, saving memory

- It enforces const-correctness, protecting against certain classes
  of bugs

The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen.  This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.

llvm-svn: 134907
2011-07-11 18:25:51 +00:00
Jim Grosbach
68759971b3 Don't require pseudo-instructions to carry encoding information.
For now this is distinct from isCodeGenOnly, as code-gen-only
instructions can (and often do) still have encoding information
associated with them. Once we've migrated all of them over to true
pseudo-instructions that are lowered to real instructions prior to
the printer/emitter, we can remove isCodeGenOnly and just use isPseudo.

llvm-svn: 134539
2011-07-06 21:33:38 +00:00
Owen Anderson
c1dcf312d1 Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0.
Patch by Jim Grosbach.

llvm-svn: 133940
2011-06-27 21:06:21 +00:00
Owen Anderson
d98b684f30 Enhance the fixed-length disassembler to support the callbacks necessary for symbolic disassembly.
llvm-svn: 129708
2011-04-18 18:42:26 +00:00
Chris Lattner
0304b82f80 Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!

llvm-svn: 129558
2011-04-15 05:18:47 +00:00
Owen Anderson
49965661d5 Ignore isCodeGenOnly instructions when generating diassembly tables.
llvm-svn: 127619
2011-03-14 20:58:49 +00:00
Owen Anderson
a2d2de33c5 Add FixedLenDecoderEmitter, the skeleton of a new disassembler emitter for fixed-length instruction encodings.
A major part of its (eventual) goal is to support a much cleaner separation between disassembly callbacks
provided by the target and the disassembler emitter itself, i.e. not requiring hardcoding of knowledge in tblgen
like the existing disassembly emitters do.

The hope is that some day this will allow us to replace the existing non-Thumb ARM disassembler and remove
some of the hacks the old one introduced to tblgen.

llvm-svn: 125966
2011-02-18 21:51:29 +00:00