Bob Wilson
438a9a1367
Add Neon VCVT instructions for f32 <-> f16 conversions.
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Clang is now providing intrinsics for these and so we need to support them
in the backend. Radar 8068427.
llvm-svn: 121902
2010-12-15 22:14:12 +00:00
Bob Wilson
24fa0b33b1
Replace NEON vabdl, vaba, and vabal intrinsics with combinations of the
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vabd intrinsic and add and/or zext operations. In the case of vaba, this
also avoids the need for a DAG combine pattern to combine vabd with add.
Update tests. Auto-upgrade the old intrinsics.
llvm-svn: 112941
2010-09-03 01:35:08 +00:00
Bob Wilson
3348d2eb50
Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply,
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add, and subtract operations with zero-extended or sign-extended vectors.
Update tests. Add auto-upgrade support for the old intrinsics.
llvm-svn: 112773
2010-09-01 23:50:19 +00:00
Bob Wilson
826a677f94
Remove NEON vmovn intrinsic, replacing it with vector truncate operations.
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Auto-upgrade the old intrinsic and update tests.
llvm-svn: 112507
2010-08-30 20:02:30 +00:00
Bob Wilson
807d004452
Remove NEON vaddl, vaddw, vsubl, and vsubw intrinsics. Instead, use llvm
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IR add/sub operations with one or both operands sign- or zero-extended.
Auto-upgrade the old intrinsics.
llvm-svn: 112416
2010-08-29 05:57:34 +00:00
Bob Wilson
c01101e76c
Add alignment arguments to all the NEON load/store intrinsics.
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Update all the tests using those intrinsics and add support for
auto-upgrading bitcode files with the old versions of the intrinsics.
llvm-svn: 112271
2010-08-27 17:13:24 +00:00
Bob Wilson
0039bc228b
Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend and
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zero-extend operations.
llvm-svn: 111614
2010-08-20 04:54:02 +00:00
Dan Gohman
8a813c4ded
Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMem
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to IntrReadWriteArgMem, as it's for reading as well as writing.
llvm-svn: 110395
2010-08-05 23:36:21 +00:00
Nate Begeman
b506e13a32
Add support for getting & setting the FPSCR application register on ARM when VFP is enabled.
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Add support for using the FPSCR in conjunction with the vcvtr instruction, for controlling fp to int rounding.
Add support for the FLT_ROUNDS_ node now that the FPSCR is exposed.
llvm-svn: 110152
2010-08-03 21:31:55 +00:00
Nate Begeman
0b0f838c32
Add builtins for ssat/usat, similar to RealView's __ssat and __usat intrinsics.
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llvm-svn: 109813
2010-07-29 22:48:09 +00:00
Nate Begeman
b24fa8b8ae
Add intrinsics __builtin_arm_qadd & __builtin_arm_qsub to allow access to the QADD & QSUB instructions.
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Behave identically to __qadd & __qsub RealView instruction intrinsics.
llvm-svn: 109770
2010-07-29 17:56:55 +00:00
Chris Lattner
4eac41e12e
[llvm_void_ty] is no longer needed for result types,
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just use an empty result list.
llvm-svn: 99346
2010-03-23 23:46:07 +00:00
Bob Wilson
641b94a562
Add new intrinsics for Neon vldN_lane and vstN_lane operations.
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llvm-svn: 79716
2009-08-22 02:28:46 +00:00
Bob Wilson
c046b62f1a
Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these as
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vector shuffles. Temporarily remove the tests for these operations until the
new implementation is working.
llvm-svn: 79579
2009-08-21 00:01:42 +00:00
Bob Wilson
e000c1a6c4
Add some comments to clarify the arguments to the vtbl and vtbx intrinsics.
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llvm-svn: 78775
2009-08-12 01:48:30 +00:00
Bob Wilson
d64e304671
Use vAny type to get rid of Neon intrinsics that differed only in whether
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the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.
If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.
llvm-svn: 78646
2009-08-11 05:39:44 +00:00
Bob Wilson
1c75a23299
Use new EVT::vAny type to combine Neon intrinsics for VPADD.
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llvm-svn: 78632
2009-08-11 01:15:26 +00:00
Bob Wilson
326491672e
Change Neon table lookup (VTBL) and table extension (VTBX) intrinsics to
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take the table vectors as separate arguments, instead of the previous
approach where they were combined into one big vector.
llvm-svn: 78525
2009-08-09 06:03:09 +00:00
Bob Wilson
54c5d7c31a
Add new intrinsics for Neon VTRN, VZIP and VUZP operations. Modeling these
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as vector shuffles did not work out well. Shuffles that produce double-wide
vectors accurately represent the operation but make it hard to do anything
with the results. I considered splitting them up into 2 shuffles, one to
write each register separately, but there doesn't seem to be a good way to
reunite them for codegen.
llvm-svn: 78437
2009-08-07 23:53:05 +00:00
Bob Wilson
355e0b70e0
Change Neon VLDn intrinsics to return multiple values instead of really
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wide vectors. Likewise, change VSTn intrinsics to take separate arguments
for each vector in a multi-vector struct. Adjust tests accordingly.
llvm-svn: 77468
2009-07-29 16:39:22 +00:00
Bob Wilson
5178063d06
Change NEON vldN/vstN intrinsics to specify "N" as an immediate operand
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instead of having a separate intrinsic for each value.
llvm-svn: 74958
2009-07-07 22:27:20 +00:00
Bob Wilson
3e85b50558
Add missing argument for vtbx intrinsic.
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llvm-svn: 74340
2009-06-26 22:27:22 +00:00
Bob Wilson
2f5abb6b29
Add intrinsics for ARM NEON vtbl and vtbx operations.
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llvm-svn: 74333
2009-06-26 21:45:05 +00:00
Bob Wilson
ff09d2879d
Swap order of arguments to vst[34]* intrinsics. This matches the order
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used by both the user-visible intrinsics defined by ARM and the
corresponding GCC builtins.
llvm-svn: 74300
2009-06-26 18:23:29 +00:00
Bob Wilson
6db76aaf10
Add support for ARM's Advanced SIMD (NEON) instruction set.
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This is still a work in progress but most of the NEON instruction set
is supported.
llvm-svn: 73919
2009-06-22 23:27:02 +00:00
Bill Wendling
9dc2bd7973
Modify the intrinsics pattern to separate out the "return" types from the
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"parameter" types. An intrinsic can now return a multiple return values like
this:
def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty],
[LLVMMatchType<0>, LLVMMatchType<0>]>;
llvm-svn: 59237
2008-11-13 09:08:33 +00:00
Chris Lattner
7a9b0bf0eb
remove attribution from a variety of miscellaneous files.
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llvm-svn: 45425
2007-12-29 22:59:10 +00:00
Lauro Ramos Venancio
d8f2190c19
[ARM] Implement __builtin_thread_pointer.
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llvm-svn: 43892
2007-11-08 17:20:05 +00:00