RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 03:53:04 +02:00
Code Issues Projects Releases Wiki Activity
37,422 Commits 4 Branches 5 Tags 704 MiB
b741ebba29
Commit Graph

8091 Commits

Author SHA1 Message Date
Chris Lattner
b741ebba29 add a note 
llvm-svn: 48064
 2008-03-09 01:08:22 +00:00
Chris Lattner
17f68a3075 Implement a readme entry, compiling 
#include <xmmintrin.h>
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}

into:
	movl	$1, %eax
	movd	%eax, %xmm0
	ret

instead of a constant pool load.

llvm-svn: 48063
 2008-03-09 01:05:04 +00:00
Chris Lattner
81deb3bc9c 1) Improve comments. 
2) Don't try to insert an i64 value into the low part of a 
   vector with movq on an x86-32 target.  This allows us to 
   compile:

__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}

into:

_doload64:
	movaps	LCPI1_0, %xmm0
	ret

instead of:

_doload64:
	subl	$28, %esp
	movl	$0, 4(%esp)
	movl	$1, (%esp)
	movq	(%esp), %xmm0
	addl	$28, %esp
	ret

llvm-svn: 48057
 2008-03-08 22:59:52 +00:00
Chris Lattner
405f2c6356 minor simplifications to this code, don't create a dead 
SCALAR_TO_VECTOR on paths that end up not using it.

llvm-svn: 48056
 2008-03-08 22:48:29 +00:00
Chris Lattner
ff9dc0af80 This one looks easy, add a note. 
llvm-svn: 48055
 2008-03-08 22:32:39 +00:00
Chris Lattner
b12697f8bb move these to the appropriate file 
llvm-svn: 48054
 2008-03-08 22:28:45 +00:00
Dale Johannesen
55d6e1a5aa More ppc32 byval handling (bug fixes). Things 
are looking pretty good now.

llvm-svn: 48043
 2008-03-08 01:41:42 +00:00
Evan Cheng
dba1dfe962 Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions. 
llvm-svn: 48042
 2008-03-08 00:58:38 +00:00
Dan Gohman
afeac8050d Add support for calls with i128 return values on ppc64. 
llvm-svn: 48041
 2008-03-08 00:19:12 +00:00
Bill Wendling
948c50e2be PPC64 passes arguments of integral type in i64 registers, not i32. Reflect this 
by promoting smaller integral values (i32 at this point) to i64, then truncating
to get the wanted size.

llvm-svn: 48030
 2008-03-07 20:49:02 +00:00
Dan Gohman
5bf464e1e6 Add support for lowering 128-bit shifts on ppc64. 
llvm-svn: 48029
 2008-03-07 20:36:53 +00:00
Dale Johannesen
3e6bacf7be Next bits of PPC byval handling. Basically functional 
but there are bugs.

llvm-svn: 48028
 2008-03-07 20:27:40 +00:00
Chris Lattner
08ec4919ea Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl). 
llvm-svn: 48027
 2008-03-07 20:18:24 +00:00
Chris Lattner
2f13ccc181 Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work 
with 32 or 64-bit operands/results.

llvm-svn: 48026
 2008-03-07 20:13:51 +00:00
Chris Lattner
aa81dc7d21 mark frem as expand for all legal fp types on x86, regardless of whether 
we're using SSE or not.  This fixes PR2122.

llvm-svn: 48006
 2008-03-07 06:36:32 +00:00
Gabor Greif
92e00c1e50 some more spelling changes 
llvm-svn: 47996
 2008-03-06 10:51:21 +00:00
Scott Michel
8dd2324903 Refine Cell's i64 constant generation code to cover more constants where the 
upper and lower 32-bits are the same (in addition to 0 and -1 previously.)

llvm-svn: 47985
 2008-03-06 04:02:54 +00:00
Andrew Lenharth
0c26f5bb94 gcc likes things spelled correctly 
llvm-svn: 47981
 2008-03-05 23:41:37 +00:00
Dale Johannesen
6bcc9808db Next bit of PPC ByVal handling; call-site code seems 
correct now.

llvm-svn: 47978
 2008-03-05 23:31:27 +00:00
Scott Michel
c29399e54e - Fix support for "special" i64 immediates that can be loaded 
using IL, ILA, et. al. v2i64 and i64 are now supported by
  the select bits (SELB) instruction.

- Add missing comparison operations (testcase forthcoming)

- More multiclass refactoring.

llvm-svn: 47973
 2008-03-05 23:02:02 +00:00
Chris Lattner
83e0b885f8 evan implemented this. 
llvm-svn: 47948
 2008-03-05 17:11:51 +00:00
Evan Cheng
a36562006a isTwoAddress = 1 -> Constraints. 
llvm-svn: 47941
 2008-03-05 08:19:16 +00:00
Evan Cheng
6c2bb7c67e PSLLWri etc. are two-address instructions. 
llvm-svn: 47940
 2008-03-05 08:11:27 +00:00
Chris Lattner
7571a88209 add a note 
llvm-svn: 47939
 2008-03-05 07:22:39 +00:00
Evan Cheng
d421708e35 Ignore debugging related instructions if they get this far. 
llvm-svn: 47934
 2008-03-05 02:34:36 +00:00
Evan Cheng
a2939a16de Rather than asserting. Dump out the MI that we are not able to encode and abort. 
llvm-svn: 47933
 2008-03-05 02:08:03 +00:00
Evan Cheng
e0b3c221ab Add a target lowering hook to control whether it's worthwhile to compress fp constant. 
For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive.

llvm-svn: 47931
 2008-03-05 01:30:59 +00:00
Andrew Lenharth
95c88272c6 64bit CAS on 32bit x86. 
llvm-svn: 47929
 2008-03-05 01:15:49 +00:00
Evan Cheng
18064ddb5b Refactor code. Remove duplicated functions that basically do the same thing as 
findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies.

llvm-svn: 47927
 2008-03-05 00:59:57 +00:00
Bill Wendling
37f5b4586a Removed spurious EnablePPCRS check. 
llvm-svn: 47918
 2008-03-04 23:27:33 +00:00
Dale Johannesen
86867d323e Move PPC lowering functions into PPCTargetLowering 
class (cosmetic).  First piece of byval implementation;
this doesn't work yet.  No functional change.

llvm-svn: 47917
 2008-03-04 23:17:14 +00:00
Bill Wendling
dc9de245cb Use a command-line option to turn register scavenging on/off for PPC. 
llvm-svn: 47915
 2008-03-04 23:13:51 +00:00
Andrew Lenharth
f5674915c5 x86-64 atomics 
llvm-svn: 47903
 2008-03-04 21:13:33 +00:00
Evan Cheng
ae414db8d2 80 column violations. 
llvm-svn: 47878
 2008-03-04 03:20:06 +00:00
Evan Cheng
139517b682 Remove -always-fold-and-in-test. 
llvm-svn: 47871
 2008-03-04 00:40:35 +00:00
Dan Gohman
ccc0bc5878 Add support for lowering i64 SRA_PARTS and friends on x86-64. 
llvm-svn: 47865
 2008-03-03 22:22:09 +00:00
Bill Wendling
8d64999daf This is the initial check-in for adding register scavenging to PPC. (Currently, 
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.

llvm-svn: 47863
 2008-03-03 22:19:16 +00:00
Devang Patel
d0d7028a2b s/isReturnStruct()/hasStructRetAttr()/g 
llvm-svn: 47857
 2008-03-03 21:46:28 +00:00
Chris Lattner
f818270d43 another random note 
llvm-svn: 47831
 2008-03-02 19:29:42 +00:00
Chris Lattner
f2a9b32eec add a note 
llvm-svn: 47830
 2008-03-02 19:27:34 +00:00
Chris Lattner
299977b5ca Evan implemented these. 
llvm-svn: 47828
 2008-03-02 18:05:14 +00:00
Chris Lattner
4c67781884 Evan implemented this. 
llvm-svn: 47827
 2008-03-02 17:56:29 +00:00
Chris Lattner
963b3c9039 add support for lvsl, fixing PR1481 
llvm-svn: 47825
 2008-03-02 08:54:27 +00:00
Chris Lattner
fdcd03cc98 add support for the sse.cmp.* intrinsics, which fixes sse.isamax with the CBE. 
llvm-svn: 47824
 2008-03-02 08:47:13 +00:00
Chris Lattner
7196bf5358 refactor intrinsic handling code out into its own method. 
llvm-svn: 47823
 2008-03-02 08:29:41 +00:00
Chris Lattner
75c409057a fix printing of undef vectors, this fixes "simple" and "build" in UnitTests/Vector. 
Now they all pass.

llvm-svn: 47820
 2008-03-02 08:14:45 +00:00
Chris Lattner
d8eeb6b1c8 insertelement got the wrong operands. 
llvm-svn: 47819
 2008-03-02 08:10:16 +00:00
Chris Lattner
e9aa391b61 Several changes: 
* Simplify handling of byval, making it easier to understand and more 
    consistent.  This fixes PR2065.
  * Clean up and simplify handling of GEPs.  I can actually understand it now!
  * Implement support for GEP'ing into vectors, this fixes
    SingleSource/UnitTests/Vector/build2 among others.

llvm-svn: 47818
 2008-03-02 08:07:24 +00:00
Chris Lattner
78f255dca8 Fix a bug I introduced in constant array and constant vector handling. 
llvm-svn: 47816
 2008-03-02 05:46:57 +00:00
Chris Lattner
96469b446d implement shufflevector. 
llvm-svn: 47815
 2008-03-02 05:41:07 +00:00