Bob Wilson
b85b3cf91f
Start converting NEON load/stores to use pseudo instructions, beginning here
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with the VST4 instructions. Until after register allocation, we want to
represent sets of adjacent registers by a single super-register. These
VST4 pseudo instructions have a single QQ or QQQQ source register operand.
They get expanded to the real VST4 instructions with 4 separate D register
operands. Once this conversion is complete, we'll be able to remove the
NEONPreAllocPass and avoid some fragile and hacky code elsewhere.
llvm-svn: 112108
2010-08-25 23:27:42 +00:00
Bruno Cardoso Lopes
28f3261dbd
Revert this for now, PUNPCKLDQ dont operate on v4f32
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llvm-svn: 112090
2010-08-25 21:26:37 +00:00
Daniel Dunbar
1a881a3eca
X86: Fix misencode of RI64mi8. This fixes OpenSSL / x86_64-apple-darwin10 / clang -O3.
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llvm-svn: 112089
2010-08-25 21:11:02 +00:00
Jim Grosbach
50dbbda454
Don't override the var from the enclosing scope.
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When doing copy/paste/modify, it's apparently rather important to remember
the 'modify' bit...
llvm-svn: 112075
2010-08-25 19:11:34 +00:00
Chris Lattner
84423f212d
zap dead code
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llvm-svn: 112073
2010-08-25 19:00:00 +00:00
Benjamin Kramer
4eb0e8bb2c
Remove dead recursive function. Yay for clang -Wunused-function.
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llvm-svn: 112060
2010-08-25 17:27:58 +00:00
Daniel Dunbar
9b7c2ce591
ARM/Thumb2: Fix a misselect in getARMCmp, when attempting to adjust a signed
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comparison that would overflow.
- The other under/overflow cases can't actually happen because the immediates
which would trigger them are legal (so we don't enter this code), but
adjusted the style to make it clear the transform is always valid.
llvm-svn: 112053
2010-08-25 16:58:05 +00:00
Eric Christopher
1bf07e75ac
Do type checks before we bother to do everything else.
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llvm-svn: 112039
2010-08-25 08:43:57 +00:00
Anton Korobeynikov
1544f79e36
Fix nasty mingw32 bug, which e.g. prevented llvm-gcc bootstrap there.
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Mark _alloca call as clobberring EFLAGS, otherwise some DCE might remove
other flags-clobberring stuff (e.g. cmp instructions) occuring after
_alloca call.
llvm-svn: 112034
2010-08-25 07:50:11 +00:00
Eric Christopher
9e3831d7a9
Reorganize load mechanisms. Handle types in a little less fixed way.
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Fix some todos. No functional change.
llvm-svn: 112031
2010-08-25 07:23:49 +00:00
Bruno Cardoso Lopes
af72dd7362
PUNPCKLDQ should also be used for v4f32
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llvm-svn: 112020
2010-08-25 02:55:40 +00:00
Bruno Cardoso Lopes
33aa4f7d1c
teach lowering to get target specific nodes for pshufd, emulating the same isel behavior for now, so we can pass all vector shuffle tests
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llvm-svn: 112017
2010-08-25 02:35:37 +00:00
Eric Christopher
a2d3859ee7
Fix predicate and add a comment.
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llvm-svn: 111981
2010-08-24 22:34:11 +00:00
Eric Christopher
5477fa47fd
Rework braindead conditionals I put in yesterday.
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llvm-svn: 111974
2010-08-24 22:07:27 +00:00
Eric Christopher
10422f70dc
Fix thumb2 mode loads to have the correct operand ordering. Add a todo
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to fix this in the port.
llvm-svn: 111973
2010-08-24 22:03:02 +00:00
Jim Grosbach
1b102f0b63
Add ARM heuristic for when to allocate a virtual base register for stack
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access. rdar://8277890&7352504
llvm-svn: 111968
2010-08-24 21:19:33 +00:00
Daniel Dunbar
b96b0c40d3
MC/X86: Tweak imul recognition, previous hack only applies for the imul form
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taking immediates.
llvm-svn: 111950
2010-08-24 19:37:56 +00:00
Daniel Dunbar
3b74f75d13
MC/X86: Add custom hack for recognizing "imul $12, %eax" and friends.
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llvm-svn: 111947
2010-08-24 19:24:18 +00:00
Daniel Dunbar
75e77b0063
MC/X86: Warn on scale factors > 1 without index register, instead of erroring,
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for 'as' compatibility.
llvm-svn: 111945
2010-08-24 19:13:38 +00:00
Jim Grosbach
0c3eb7ca50
Move enabling the local stack allocation pass into the target where it belongs.
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For now it's still a command line option, but the interface to the generic
code doesn't need to know that.
llvm-svn: 111942
2010-08-24 19:05:43 +00:00
Jim Grosbach
a110ecf96a
add ARM cmd line option to force always using virtual base regs when possible.
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Intended to help ease reproducing problems by increasing base register usage
after heuristics for only using the when needed are in place.
llvm-svn: 111930
2010-08-24 18:04:52 +00:00
Dan Gohman
e400c660e4
Fix X86's isLegalAddressingMode to recognize that static addresses
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need not be RIP-relative in small mode.
llvm-svn: 111917
2010-08-24 15:55:12 +00:00
Kalle Raiskila
1be8a5f947
Fix SPU BE to use all the available return registers.
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llc used to assert on the added testcase.
llvm-svn: 111911
2010-08-24 11:50:48 +00:00
Kalle Raiskila
ef9e592448
Remove some dead code from SPU BE that remained
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from 64bit vector support.
llvm-svn: 111910
2010-08-24 11:05:51 +00:00
Bruno Cardoso Lopes
7939025262
Use pshufhw and pshuflw in more cases and fix getTargetShuffleNode number of arguments
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llvm-svn: 111890
2010-08-24 01:16:15 +00:00
Bill Wendling
c92b4d86ad
Add comments for what the condition code symbols mean.
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llvm-svn: 111889
2010-08-24 01:11:30 +00:00
Eric Christopher
c2ed70d52b
Update comment.
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llvm-svn: 111887
2010-08-24 01:10:52 +00:00
Eric Christopher
5f3382bacc
Fix the opcode and the operands for the load instruction.
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llvm-svn: 111885
2010-08-24 01:10:04 +00:00
Eric Christopher
5d1289db95
Add register class hack that needs to go away, but makes it more obvious
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that it needs to go away. Use loadRegFromStackSlot where possible.
Also, remember to update the value map.
llvm-svn: 111883
2010-08-24 00:50:47 +00:00
Eric Christopher
696d6ee9d7
Add some more debugging code, make it more obvious that RegOffset is
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getting an address for an object and select some default values.
llvm-svn: 111871
2010-08-24 00:07:24 +00:00
Eric Christopher
a1652c6ea6
Don't need the extra register here.
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llvm-svn: 111864
2010-08-23 23:28:04 +00:00
Eric Christopher
2f01adebca
Add some more "get address into register" code and a more TODOs/FIXMEs.
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llvm-svn: 111860
2010-08-23 23:14:31 +00:00
Eric Christopher
7ec47db6b2
Add an ARMFunctionInfo member and use it.
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llvm-svn: 111854
2010-08-23 22:32:45 +00:00
Eric Christopher
e0d09e27f8
Start getting ARM loads/address computation going.
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llvm-svn: 111850
2010-08-23 21:44:12 +00:00
Bruno Cardoso Lopes
ed9ff8d8d0
Start using target speficic nodes for shuffles: pshufhw and pshuflw
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llvm-svn: 111837
2010-08-23 20:41:02 +00:00
Gabor Greif
6bd4b1cc6c
tyops
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llvm-svn: 111835
2010-08-23 20:30:51 +00:00
Chris Lattner
f0f35c4aea
Add a new llvm.x86.int intrinsic, allowing access to the
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x86 int and int3 instructions. Patch by Peter Housel!
llvm-svn: 111831
2010-08-23 19:39:25 +00:00
Chris Lattner
f4dfc7aaab
random improvement for variable shift codegen.
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llvm-svn: 111813
2010-08-23 17:30:29 +00:00
Anton Korobeynikov
a68e2a53a1
Revert invalid r111792. Jump tables are not broken on x86-64 / coff,
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it's COFF emitter which does not support differences of two symbols
(and needs to be fixed). GAS is pretty fine with code produced.
llvm-svn: 111801
2010-08-23 07:38:51 +00:00
Michael J. Spencer
c52ac23659
Workaround broken jump tables on x86-64 COFF.
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llvm-svn: 111792
2010-08-23 04:45:37 +00:00
Anton Korobeynikov
c3294e6abe
Use rip-rel addressing on win64 by default. For this we just
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defaults to small pic code model.
llvm-svn: 111741
2010-08-21 17:21:11 +00:00
Michael J. Spencer
18689045ce
MC: Add partial x86-64 support to COFF.
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llvm-svn: 111728
2010-08-21 05:58:13 +00:00
Dan Gohman
30b8e6cfd2
Fix x86 fast-isel's cmp+branch folding to avoid folding when the
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comparison is in a different basic block from the branch. In such
cases, the comparison's operands may not have initialized virtual
registers available.
llvm-svn: 111709
2010-08-21 02:32:36 +00:00
Bruno Cardoso Lopes
1998fbbf1a
Prepare LowerVECTOR_SHUFFLEv8i16 to use x86 target specific nodes directly
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llvm-svn: 111704
2010-08-21 01:32:18 +00:00
Bruno Cardoso Lopes
28d9071635
This is the first step towards refactoring the x86 vector shuffle code. The
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general idea here is to have a group of x86 target specific nodes which are
going to be selected during lowering and then directly matched in isel.
The commit includes the addition of those specific nodes and a *bunch* of
patterns, and incrementally we're going to switch between them and what we
have right now. Both the patterns and target specific nodes can change as
we move forward with this work.
llvm-svn: 111691
2010-08-20 22:55:05 +00:00
Bill Wendling
163660135e
Create the new linker type "linker_private_weak_def_auto".
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It's similar to "linker_private_weak", but it's known that the address of the
object is not taken. For instance, functions that had an inline definition, but
the compiler decided not to inline it. Note, unlike linker_private and
linker_private_weak, linker_private_weak_def_auto may have only default
visibility. The symbols are removed by the linker from the final linked image
(executable or dynamic library).
llvm-svn: 111684
2010-08-20 22:05:50 +00:00
Bob Wilson
0039bc228b
Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend and
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zero-extend operations.
llvm-svn: 111614
2010-08-20 04:54:02 +00:00
Eric Christopher
e082792357
Fix loop conditionals (MO.isDef() asserts that it's a reg) and
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move some constraints around.
llvm-svn: 111594
2010-08-20 00:36:24 +00:00
Eric Christopher
df3a3f5e3e
Add a couple of random comments.
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llvm-svn: 111592
2010-08-20 00:20:31 +00:00
Jim Grosbach
4e6f40561f
Better handling of offsets on frame index references. rdar://8277890
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llvm-svn: 111585
2010-08-19 23:52:25 +00:00