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Commit Graph

24927 Commits

Author SHA1 Message Date
Evan Cheng
5bf702d20a Support x86 specific inline asm modifier 'J'.
llvm-svn: 56483
2008-09-22 23:57:37 +00:00
Dan Gohman
28970ed355 Fix the alignment of loads from constant pool entries when the
load address has an offset from the base of the constant pool
entry.

llvm-svn: 56479
2008-09-22 22:40:08 +00:00
Devang Patel
c7fc5ed65f Add hasNote() to check note associated with a function.
llvm-svn: 56477
2008-09-22 22:32:29 +00:00
Evan Cheng
0cfe303607 Livestacks really does preserve everything.
llvm-svn: 56476
2008-09-22 22:26:15 +00:00
Evan Cheng
1ded8b6ad6 Instead of setPreservesAll, just mark them preseving machine loop info and machine dominators.
llvm-svn: 56475
2008-09-22 22:21:38 +00:00
Owen Anderson
67df9bc5b8 Significant improvements to the logic for merging live intervals. This code can't
just use LI::MergeValueAsValue, as its behavior in the presence of overlapping ranges
isn't what StrongPHIElimination wants.

llvm-svn: 56472
2008-09-22 21:58:58 +00:00
Dale Johannesen
3722f4c14c Make log, log2, log10, exp, exp2 use Expand by
default.

llvm-svn: 56471
2008-09-22 21:57:32 +00:00
Evan Cheng
3bcf0cdd72 Mark several codegen passes as preserving all analysis.
llvm-svn: 56469
2008-09-22 20:58:04 +00:00
Dale Johannesen
375ba5ee63 More refactoring. Yawn.
llvm-svn: 56468
2008-09-22 20:51:30 +00:00
Dale Johannesen
a28dd108a4 Refactor FP intrinisic setup. Per review feedback.
llvm-svn: 56456
2008-09-22 19:51:58 +00:00
Oscar Fuentes
e51d9c0c3a CMake build system: support for parallel builds.
llvm-svn: 56453
2008-09-22 18:21:51 +00:00
Evan Cheng
638ae1be58 Per review feedback: Only perform
(srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c))
etc. when both "trunc" and "and" have single uses.

llvm-svn: 56452
2008-09-22 18:19:24 +00:00
Arnold Schwaighofer
49f49e2086 Change the calling convention used when tail call optimization is enabled from CC_X86_32_TailCall to CC_X86_32_FastCC.
llvm-svn: 56436
2008-09-22 14:50:07 +00:00
Oscar Fuentes
0f25988689 Initial support for the CMake build system.
llvm-svn: 56419
2008-09-22 01:08:49 +00:00
Bill Wendling
3ee08ff81e Add helper function to get a 32-bit floating point constant. No functionality change.
llvm-svn: 56418
2008-09-22 00:44:35 +00:00
Chris Lattner
6e5b4c609c Fold immediates into X86 shifts with fast isel. This generates:
sarl    $3, %ecx

instead of:

movl    $3, %ecx
sarl    %cl, %edx

This shrinks fast isel 176.gcc by about 2000 instructions (.3%)

llvm-svn: 56413
2008-09-21 21:44:29 +00:00
Dan Gohman
98a22f8a8f Factor out code into HandleVirtRegDef, for consistency with
Handle{Virt,Phys}Reg{Def,Use}. Remove a redundant check
for register zero, and redundant checks for isPhysicalRegister.

llvm-svn: 56412
2008-09-21 21:11:41 +00:00
Dan Gohman
c8477ceabe Instead of building a list and sorting it just to find a maximum element,
compute the maximum element directly.

llvm-svn: 56411
2008-09-21 21:01:49 +00:00
Owen Anderson
981113c401 Fetch the starting index of the block when assigning intervals. This gets live-in indices
correct in the presence of things like EH labels.

llvm-svn: 56410
2008-09-21 20:43:24 +00:00
Chris Lattner
01cab96cba don't print GlobalAddressSDNode's with an offset of zero as "foo0".
llvm-svn: 56399
2008-09-21 18:38:31 +00:00
Chris Lattner
c018045520 add a note
llvm-svn: 56391
2008-09-20 19:17:53 +00:00
Duncan Sands
38b44d2a40 Implement review feedback from Devang: make use
of mayReadFromMemory and mayWriteToMemory.

llvm-svn: 56387
2008-09-20 16:45:58 +00:00
Dale Johannesen
4a0054dc9a Teach coalescer about earlyclobber bits.
Check bits for preferred register.

llvm-svn: 56384
2008-09-20 02:03:04 +00:00
Evan Cheng
270178bdda Fix PR2808. When regalloc runs out of register, it spill a physical register around the live interval being allocated. Do not continue to try to spill another register, just grab the physical register and move on.
llvm-svn: 56381
2008-09-20 01:28:05 +00:00
Evan Cheng
6a86ec1ef0 No need to print function stubs for Mac OS X 10.5 and up. Linker will handle it.
llvm-svn: 56378
2008-09-20 00:13:45 +00:00
Evan Cheng
7bcd8409b7 80 column violation.
llvm-svn: 56377
2008-09-20 00:13:08 +00:00
Dan Gohman
af1eeb6421 Fix a FastISel GlobalVariable CSE bug.
llvm-svn: 56376
2008-09-19 23:42:04 +00:00
Evan Cheng
23e36297d6 Continue after removing the current MI.
llvm-svn: 56372
2008-09-19 22:49:39 +00:00
Dan Gohman
f66b3277d3 Refactor X86SelectConstAddr, folding it into X86SelectAddress. This
results in better code for globals. Also, unbreak the local CSE for
GlobalValue stub loads.

llvm-svn: 56371
2008-09-19 22:16:54 +00:00
Dale Johannesen
312df3aa6d Make earlyclobber stuff work when virtual regs
have previously been assigned conflicting physreg.

llvm-svn: 56364
2008-09-19 18:52:31 +00:00
Evan Cheng
14493ffe78 Re-materalized definition instructions may be dead. Whack them.
llvm-svn: 56352
2008-09-19 17:38:47 +00:00
Gabor Greif
984ba5a313 backing out my last commit, it was not intended to go on the trunk
llvm-svn: 56349
2008-09-19 15:13:20 +00:00
Gabor Greif
67fa076542 first shot at removing Use::Val
untested, Use::swap() is definitely not done yet

llvm-svn: 56348
2008-09-19 15:03:57 +00:00
Duncan Sands
b2b5ddfaf6 Remove the MarkModRef pass (use AddReadAttrs instead).
Unfortunately this means removing one regression test
of GlobalsModRef because I couldn't work out how to
perform it without MarkModRef.

llvm-svn: 56342
2008-09-19 08:23:44 +00:00
Duncan Sands
c2ff9ca568 Add a new pass AddReadAttrs which works out which functions
can get the readnone/readonly attributes, and gives them it.
The plan is to remove markmodref (which did the same thing
by querying GlobalsModRef) and delete the analogous
functionality from GlobalsModRef.

llvm-svn: 56341
2008-09-19 08:17:05 +00:00
Dale Johannesen
214ddc92d0 Remove AsmThatEarlyClobber etc. from LiveIntervalAnalysis
and redo as linked list walk.  Logic moved into RA.
Per review feedback.

llvm-svn: 56326
2008-09-19 01:02:35 +00:00
Devang Patel
1e7ddf5d31 splitLoop does not handle split condition EQ.
Fixes PR 2805

llvm-svn: 56321
2008-09-18 23:45:14 +00:00
Dan Gohman
71b1f15917 Address-mode folding for X86FastISel. It's pretty basic, but it
catches a fair number of common cases. Note that this currently
causes Fast-ISel to leave behind lots of dead instructions.
Those will be dealt with in subsequent commits.

llvm-svn: 56320
2008-09-18 23:23:44 +00:00
Bill Wendling
aadf9b22a7 Decrementing the iterator here could be wrong if the worklist is empty after the "erase".
Thanks to Ji Young Park for the patch!

llvm-svn: 56316
2008-09-18 23:04:18 +00:00
Devang Patel
201223af46 Try to place hoisted instructions befoe icmp instruction.
llvm-svn: 56315
2008-09-18 22:50:42 +00:00
Evan Cheng
bcd694a1b4 Somehow RegAllocLinearScan is keeping two pointers to MachineRegisterInfo.
llvm-svn: 56314
2008-09-18 22:38:47 +00:00
Dan Gohman
e1c4ad399a Simplify this code. The FastISel class has its own TD member.
llvm-svn: 56311
2008-09-18 18:26:43 +00:00
Dan Gohman
9dc56fbe40 Don't consider instructions with implicit physical register
defs to be necessarily live.

llvm-svn: 56310
2008-09-18 18:22:32 +00:00
Dan Gohman
b7c5b0f44b Add a new "fast" scheduler. This is currently basically just a
copy of the BURRList scheduler, but with several parts ripped
out, such as backtracking, online topological sort maintenance
(needed by backtracking), the priority queue, and Sethi-Ullman
number computation and maintenance (needed by the priority
queue). As a result of all this, it generates somewhat lower
quality code, but that's its tradeoff for running about 30%
faster than list-burr in -fast mode in many cases.

This is somewhat experimental. Moving forward, major pieces of
this can be refactored with pieces in common with
ScheduleDAGRRList.cpp.

llvm-svn: 56307
2008-09-18 16:26:26 +00:00
Evan Cheng
a0459a1c5a Preliminary support for systems which require changing JIT memory regions privilege from read / write to read / executable.
llvm-svn: 56303
2008-09-18 07:54:21 +00:00
Evan Cheng
6acdef5d11 Duh. Default to ARMCC::AL (always).
llvm-svn: 56301
2008-09-18 07:28:19 +00:00
Evan Cheng
99a186e39f Clean up.
llvm-svn: 56300
2008-09-18 07:27:23 +00:00
Evan Cheng
b44e839f76 Cosmetic.
llvm-svn: 56299
2008-09-18 07:24:33 +00:00
Dan Gohman
5fbd0e95f3 FastISel: For calls, prefer using the callee's address as a constant
over having it in a register. And wait until after checking type
legality before requesting that the callee address be placed in a
register. Also, fix support for calls with void return type.

This speeds up fast-isel isel time by about 15% and reduces
instruction counts by about 3% overall on certain testcases. It also
changes many indirect calls to direct calls.

llvm-svn: 56292
2008-09-17 21:18:49 +00:00
Dale Johannesen
99091ed94f Add a bit to mark operands of asm's that conflict
with an earlyclobber operand elsewhere.  Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way 
that conflicts with an earlyclobber.  See also comments.

llvm-svn: 56290
2008-09-17 21:13:11 +00:00
Evan Cheng
d3225118a6 Unallocatable registers do not have live intervals.
llvm-svn: 56287
2008-09-17 18:36:25 +00:00
Devang Patel
88efee2dcc Do not hoist instruction above branch condition. The instruction may use branch condition.
llvm-svn: 56286
2008-09-17 18:21:49 +00:00
Devang Patel
50c22bf69b Do not ignore iv uses outside the loop.
This one slipped through cracks very well.

llvm-svn: 56284
2008-09-17 17:53:47 +00:00
Dan Gohman
4bef47e8c3 Don't worry about clobbering physical register defs that aren't used.
llvm-svn: 56281
2008-09-17 15:25:49 +00:00
Evan Cheng
f2c04a10e6 Fix addrmode1 instruction encodings; fix bx_ret encoding.
llvm-svn: 56277
2008-09-17 07:53:38 +00:00
Evan Cheng
d268288d39 Specify instruction encoding using range list to avoid endianess issues.
llvm-svn: 56276
2008-09-17 07:16:21 +00:00
Dan Gohman
9475c22537 Simplify and generalize X86DAGToDAGISel::CanBeFoldedBy, and draw
up some new ascii art to illustrate what it does. This change
currently has no effect on generated code.

llvm-svn: 56270
2008-09-17 01:39:10 +00:00
Dan Gohman
d0c6cb65e8 Add a new MachineInstr-level DCE pass. It is very simple, and is intended to
be used with fast-isel.

llvm-svn: 56268
2008-09-17 00:43:24 +00:00
Bill Wendling
b2701e541c Add trampoline support to PPC. GCC simply calls the "__trampoline_setup"
function with appropriate parameters. This allows us to support blocks on PPC.

llvm-svn: 56267
2008-09-17 00:30:57 +00:00
Evan Cheng
6cfbecd1fa When converting a CopyFromReg to a copy instruction, use the register class of its uses to determine the right destination register class of the copy. This is important for targets where a physical register may belong to multiple register classes.
llvm-svn: 56258
2008-09-16 23:12:11 +00:00
Dan Gohman
9cbb3f591a Change SelectionDAG::getConstantPool to always set the alignment of the
ConstantPoolSDNode, using the target's preferred alignment for the
constant type.

In LegalizeDAG, when performing loads from the constant pool, the
ConstantPoolSDNode's alignment is used in the calls to getLoad and
getExtLoad.

This change prevents SelectionDAG::getLoad/getExtLoad from incorrectly
choosing the ABI alignment for constant pool loads when Alignment == 0.
The incorrect alignment is only a performance issue when ABI alignment
does not equal preferred alignment (i.e., on x86 it was generating
MOVUPS instead of MOVAPS for v4f32 constant loads when the default ABI
alignment for 128bit vectors is forced to 1 byte.)

Patch by Paul Redmond!

llvm-svn: 56253
2008-09-16 22:05:41 +00:00
Bill Wendling
932818c75a Reverting r56249. On further investigation, this functionality isn't needed.
Apologies for the thrashing.

llvm-svn: 56251
2008-09-16 21:48:12 +00:00
Dan Gohman
6da3227304 Include the alignment value when displaying ConstantPoolSDNodes.
llvm-svn: 56250
2008-09-16 21:18:22 +00:00
Bill Wendling
1a240c8033 - Change "ExternalSymbolSDNode" to "SymbolSDNode".
- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol

These changes pave the way to allowing SymbolSDNodes with non-external linkage.

llvm-svn: 56249
2008-09-16 21:12:30 +00:00
Dan Gohman
f89b35c261 Fix these comments to reflect current reality. Surprisingly,
MachineConstantPool::getConstantPoolIndex actually expects
a log2-encoded alignment.

llvm-svn: 56248
2008-09-16 20:45:53 +00:00
Dan Gohman
885e592e9b Finally re-apply r46959. This is made feasible by the combination
of r56230, r56232, and r56246.

llvm-svn: 56247
2008-09-16 18:52:57 +00:00
Dan Gohman
c598e29a1c Improve instcombine's handling of integer min and max in two ways:
- Recognize expressions like "x > -1 ? x : 0" as min/max and turn them
   into expressions like "x < 0 ? 0 : x", which is easily recognizable
   as a min/max operation.
 - Refrain from folding expression like "y/2 < 1" to "y < 2" when the
   comparison is being used as part of a min or max idiom, like
   "y/2 < 1 ? 1 : y/2". In that case, the division has another use, so
   folding doesn't eliminate it, and obfuscates the min/max, making it
   harder to recognize as a min/max operation.

These benefit ScalarEvolution, CodeGen, and anything else that wants to
recognize integer min and max.

llvm-svn: 56246
2008-09-16 18:46:06 +00:00
Evan Cheng
f80fc084ef AllocateRWXMemory -> AllocateRWX.
llvm-svn: 56244
2008-09-16 17:28:18 +00:00
Dan Gohman
37457ca74b Don't take the time to CheckDAGForTailCallsAndFixThem when tail calls
are not enabled. Instead just omit the tail call flag when calls are
created.

llvm-svn: 56235
2008-09-16 01:42:28 +00:00
Dan Gohman
54ef20348e Re-enables the new vector select in the bitcode reader, by modifying the
bitcode reader/writer as follows:

- add and use new bitcode FUNC_CODE_INST_VSELECT to handle the llvm
select opcode using either i1 or [N x i1] as the selector.
- retain old BITCODE FUNC_CODE_INST_SELECT in the bitcode reader to
handle select on i1 for backwards compatibility with existing bitcode
files.
- re-enable the vector-select.ll test program.

Also, rename the recently added bitcode opcode FUNC_CODE_INST_VCMP to
FUNC_CODE_INST_CMP2 and make the bitcode writer use it to handle
fcmp/icmp on scalars or vectors. In the bitcode writer, use
FUNC_CODE_INST_CMP for vfcmp/vicmp only. In the bitcode reader, have
FUNC_CODE_INST_CMP handle icmp/fcmp returning bool, for backwards
compatibility with existing bitcode files.

Patch by Preston Gurd!

llvm-svn: 56233
2008-09-16 01:01:33 +00:00
Dan Gohman
0045cec2ba Teach ScalarEvolution to consider loop preheaders in the search for
an if statement that guards a loop, to allow indvars to avoid smax
operations in more situations.

llvm-svn: 56232
2008-09-15 22:18:04 +00:00
Owen Anderson
553caa6ed4 Live intervals for live-in registers should begin at the beginning of a basic block, not at the first
instruction.  Also, their valno's should have an unknown def.  This has no effect currently, but was
causing issues when StrongPHIElimination was enabled.

llvm-svn: 56231
2008-09-15 22:00:38 +00:00
Dan Gohman
faa15214e0 Teach LSR to optimize away SMAX operations for tripcounts in common
cases.  See the comment above OptimizeSMax for the full story, and
the testcase for an example. This cancels out a pessimization
commonly attributed to indvars, and will allow us to lift some of
the artificial throttles in indvars, rather than add new ones.

llvm-svn: 56230
2008-09-15 21:22:06 +00:00
Bruno Cardoso Lopes
f6ad396dfa Fixed Bug 2751
http://llvm.org/bugs/show_bug.cgi?id=2751

Abicall was enabled even when static code model was provided 
in the command line.
The correct behavior is to disable abicall when static is
specified.

llvm-svn: 56228
2008-09-15 21:06:55 +00:00
Dan Gohman
f38d63884f Re-enable SelectionDAG CSE for calls. It matters in the case of
libcalls, as in this testcase on ARM.

llvm-svn: 56226
2008-09-15 19:46:03 +00:00
Evan Cheng
db1693cb14 Correctly update kill infos after extending a live range and merge 2 val#'s; fix 56165 - do not mark val# copy field if the copy does not define the val#.
llvm-svn: 56199
2008-09-15 06:28:41 +00:00
Dan Gohman
6418cb3998 Fix WriteAsOperand to not emit a leading space character. Adjust
its callers to emit a space character before calling it when a
space is needed.

This fixes several spurious whitespace issues in
ScalarEvolution's debug dumps. See the test changes for
examples.

This also fixes odd space-after-tab indentation in the output
for switch statements, and changes calls from being printed like
this:
  call void @foo( i32 %x )
to this:
  call void @foo(i32 %x)

llvm-svn: 56196
2008-09-14 17:21:12 +00:00
Dale Johannesen
57fc1bdfdc adjust last patch per review feedback
llvm-svn: 56194
2008-09-14 01:44:36 +00:00
Dan Gohman
fa32c7c6d9 Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.

llvm-svn: 56189
2008-09-13 17:58:21 +00:00
Duncan Sands
8d5640ac90 Fix PR2792: treat volatile loads as writing memory somewhere.
Treat stores as reading memory, just to play safe.

llvm-svn: 56188
2008-09-13 12:45:50 +00:00
Evan Cheng
63b98ccd5e Fix random abort.
llvm-svn: 56184
2008-09-13 01:55:59 +00:00
Dan Gohman
3450a8252f Define CallSDNode, an SDNode subclass for use with ISD::CALL.
Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.

And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.

CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.

llvm-svn: 56183
2008-09-13 01:54:27 +00:00
Evan Cheng
775a37e4b4 Typo.
llvm-svn: 56182
2008-09-13 01:44:01 +00:00
Evan Cheng
200cdea934 Rely on instruction format to determine so_reg operand for now.
llvm-svn: 56181
2008-09-13 01:38:29 +00:00
Evan Cheng
0a3a595612 Revert 56176. All those instruction formats are still needed.
llvm-svn: 56180
2008-09-13 01:35:33 +00:00
Evan Cheng
1ac0a5f278 Accidentially flipped the condition.
llvm-svn: 56179
2008-09-13 01:29:57 +00:00
Evan Cheng
d68f2947a9 Add debug dumps.
llvm-svn: 56178
2008-09-13 01:15:21 +00:00
Evan Cheng
18fd8337b3 Eliminate unnecessary instruction formats.
llvm-svn: 56176
2008-09-12 23:15:39 +00:00
Evan Cheng
66e7651a16 Addrmode 1 S bit can be dynamically set. Look for CPSR def.
llvm-svn: 56172
2008-09-12 22:45:55 +00:00
Evan Cheng
adf6720626 Rewrite address mode 1 code emission routines.
llvm-svn: 56171
2008-09-12 22:01:15 +00:00
Evan Cheng
07046dae41 On some targets, non-move instructions can become move instructions because of coalescing. e.g.
vr2 = OR vr0, vr1
=>
vr2 = OR vr1, vr1   // after coalescing vr0 with vr1

Update the value# of the destination register with the copy instruction if that happens.

llvm-svn: 56165
2008-09-12 18:13:14 +00:00
Dan Gohman
082879cfde Change ConstantSDNode and ConstantFPSDNode to use ConstantInt* and
ConstantFP* instead of APInt and APFloat directly.

This reduces the amount of time to create ConstantSDNode
and ConstantFPSDNode nodes when ConstantInt* and ConstantFP*
respectively are already available, as is the case in
SelectionDAGBuild.cpp. Also, it reduces the amount of time
to legalize constants into constant pools, and the amount of
time to add ConstantFP operands to MachineInstrs, due to
eliminating ConstantInt::get and ConstantFP::get calls.

It increases the amount of work needed to create new constants
in cases where the client doesn't already have a ConstantInt*
or ConstantFP*, such as legalize expanding 64-bit integer constants
to 32-bit constants. And it adds a layer of indirection for the
accessor methods. But these appear to be outweight by the benefits
in most cases.

It will also make it easier to make ConstantSDNode and
ConstantFPNode more consistent with ConstantInt and ConstantFP.

llvm-svn: 56162
2008-09-12 18:08:03 +00:00
Dale Johannesen
6395da3510 Pass "earlyclobber" bit through to machine
representation; coalescer and RA need to know
about it.  No functional change.

llvm-svn: 56161
2008-09-12 17:49:03 +00:00
Dan Gohman
89660301e3 Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159
2008-09-12 16:56:44 +00:00
Duncan Sands
94a4573005 Rather than marking all internal globals "Ref"
when a readonly declaration is called, set a
flag.  This is faster and uses less memory.
In theory it is less accurate, because before
only those internal globals that were read
by someone were being marked "Ref", but now
all are.  But in practice, thanks to other
passes, all internal globals of the kind
considered here will be both read and stored
to: those only read will have been turned
into constants, and those only stored to will
have been deleted.

llvm-svn: 56143
2008-09-12 07:29:58 +00:00
Dale Johannesen
fbc17046ff The sequence for ppcf128 compares was not IEEE
safe in the presence of NaNs.

llvm-svn: 56136
2008-09-12 00:30:56 +00:00
Dan Gohman
0b6d3a9a9b On 64-bit targets, change 32-bit getelementptr indices to be 64-bit
getelementptr indices, inserting an explicit cast if necessary.
This helps expose the sign-extension operation to other optimizations.

llvm-svn: 56133
2008-09-11 23:06:38 +00:00
Dan Gohman
5e154a591d Fix a vectorshuffle instcombine bug introduced by r55995.
Patch by Nicolas Capens!

llvm-svn: 56129
2008-09-11 22:47:57 +00:00
Jim Grosbach
a25a322741 udpate header comment: s/VP/VFP/
llvm-svn: 56126
2008-09-11 21:41:29 +00:00
Arnold Schwaighofer
adfb111f10 When tailcallopt is enabled all fastcc calls must have an aligned argument stack size. Add a test case.
llvm-svn: 56119
2008-09-11 20:28:43 +00:00