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7376 Commits

Author SHA1 Message Date
Dan Gohman
74a435e9f1 The upper argument of ConstantRange is exclusive, not inclusive. 
llvm-svn: 76492
 2009-07-20 22:34:18 +00:00
David Greene
1ac6d4ac0e Re-apply 75490, 75806 and 76177 with fixes and tests. Efficiency comes 
next.

llvm-svn: 76486
 2009-07-20 22:02:59 +00:00
Evan Cheng
919f5c5559 Forgot this test earlier. 
llvm-svn: 76485
 2009-07-20 21:46:42 +00:00
Dan Gohman
d2ad3e183b Assembly and Bitcode support for unsigned/signed overflow flags and 
exact sdiv flags.

llvm-svn: 76475
 2009-07-20 21:19:07 +00:00
Evan Cheng
2bac9b0d83 Use TII->findCommutedOpIndices to find the commute operands (rather than guessing). 
llvm-svn: 76472
 2009-07-20 21:16:08 +00:00
Kevin Enderby
f1c0daa6a7 Removed the DumpSymbolsandMacros and LoadSymbolsandMacros MCStreamer API as 
the parsing of the .dump and .load should be done in the assembly parser and
not have any need for an MCStreamer API.  Changed the code for now so these
just produce an error saying these specific directives are not yet implemented
since they are likely no longer used and may never need to be implemented.

llvm-svn: 76462
 2009-07-20 20:25:37 +00:00
Evan Cheng
0048e876c3 Fix some sub-reg coalescing bugs where the coalescer wasn't updating the resulting interval's register class. 
llvm-svn: 76458
 2009-07-20 19:47:55 +00:00
Dan Gohman
00b05492f1 Revert the addition of hasNoPointerOverflow to GEPOperator. 
Getelementptrs that are defined to wrap are virtually useless to
optimization, and getelementptrs that are undefined on any kind
of overflow are too restrictive -- it's difficult to ensure that
all intermediate addresses are within bounds. I'm going to take
a different approach.

Remove a few optimizations that depended on this flag.

llvm-svn: 76437
 2009-07-20 17:43:30 +00:00
Evan Cheng
e5d229f7ac xfail for now. 
llvm-svn: 76423
 2009-07-20 15:33:09 +00:00
Chris Lattner
eac40b1473 implement a new magic global "llvm.compiler.used" which is like llvm.used, but 
doesn't cause ".no_dead_strip" to be emitted on darwin.

llvm-svn: 76399
 2009-07-20 06:14:25 +00:00
Evan Cheng
7377d0cb7c Restore AsmWriterEmitter.cpp back to 74742. The recent changes broke Thumb. 
llvm-svn: 76398
 2009-07-20 06:10:07 +00:00
Daniel Dunbar
46389b3660 This test should be run with -m32. 
llvm-svn: 76382
 2009-07-19 22:44:03 +00:00
Jakob Stoklund Olesen
96f9a917c8 Fix http://llvm.org/bugs/show_bug.cgi?id=4583 
Inline asm instructions may have additional <imp-def,kill> register operands.
These operands are not marked with a flag like the normal asm operands, so we
must not assert that there is a flag.

llvm-svn: 76373
 2009-07-19 19:09:59 +00:00
Eli Friedman
e507c1afaa Canonicalize bitcasts between types like <1 x i64> and i64 to 
insertelement/extractelement.

I'm not entirely sure this is precisely what we want to do: should we 
prefer bitcast(insertelement) or insertelement(bitcast)?  Similarly. should we 
prefer extractelement(bitcast) or bitcast(extractelement)?

llvm-svn: 76345
 2009-07-18 23:06:53 +00:00
Eli Friedman
debc43cb11 Back out 76300; apparently the preference is to canonicalize the other 
way (bitcast -> insert/extractelement).

llvm-svn: 76325
 2009-07-18 19:04:16 +00:00
Eli Friedman
65a5fe312a Add combine: X sdiv (1 << Y) -> X udiv (1 << Y) when X doesn't have the 
sign bit set.

llvm-svn: 76304
 2009-07-18 09:53:21 +00:00
Eli Friedman
f1878fcda1 Canonicalize insert/extractelement from single-element vectors into 
bitcasts.

It would also be possible to canonicalize the other way; does anyone 
have a preference?

llvm-svn: 76300
 2009-07-18 09:07:47 +00:00
Eli Friedman
7b1597133d Fix simplifylibcalls memset recognition to work on 64-bit platforms 
where int is 32 bits.

llvm-svn: 76293
 2009-07-18 08:34:51 +00:00
Evan Cheng
a19ee1bb42 Catch more coalescing opportunities. 
llvm-svn: 76282
 2009-07-18 04:52:23 +00:00
Evan Cheng
84f06f0ee6 Enable cross register class coalescing. 
llvm-svn: 76281
 2009-07-18 02:10:10 +00:00
Evan Cheng
92fc255bb4 Fix pr4552. Stack slot coloring with register must take care not to generate illegal ams. 
llvm-svn: 76258
 2009-07-17 22:42:51 +00:00
Daniel Dunbar
ab1316fbaf llvm-mc: Add -triple, and start fetching the target asm printer. 
llvm-svn: 76257
 2009-07-17 22:38:58 +00:00
Evan Cheng
67ccedff04 Fix x86 inline ams 'q' constraint support. In 32-bit mode, it's just like 'Q', i.e. EAX, EDX, ECX, EBX. In 64-bit mode, it just means all the i64r registers. Yeah, that makes sense. 
llvm-svn: 76248
 2009-07-17 22:13:25 +00:00
Chris Lattner
fb1ff2b993 rename test. 
llvm-svn: 76197
 2009-07-17 18:05:55 +00:00
Duncan Sands
c77e727d4f Testcase for PR4214. 
llvm-svn: 76174
 2009-07-17 11:44:20 +00:00
Eli Friedman
fde598545c Make promotion in operation legalization for SETCC work correctly. 
llvm-svn: 76153
 2009-07-17 05:16:04 +00:00
Anton Korobeynikov
dc39f4fff8 Emit cross regclass register moves for thumb2. 
Minor code duplication cleanup.

llvm-svn: 76124
 2009-07-16 23:26:06 +00:00
Dale Johannesen
e08bda67c2 Assume an inline asm might be a call, so we get 
stack alignment right when it is.  This is not
ideal but conservatively correct.  Adjust a test
to compensate for changed stack offset value.
gcc.apple/asm-block-57.c

llvm-svn: 76120
 2009-07-16 22:34:45 +00:00
David Greene
a2c98dd402 Emit line numbers in asm comments when available. 
llvm-svn: 76117
 2009-07-16 22:24:20 +00:00
Jakob Stoklund Olesen
4a0d996780 Teach MachineInstr::isRegTiedToDefOperand() to correctly parse inline asm operands. 
The inline asm operands must be parsed from the first flag, you cannot assume
that an immediate operand preceeding a register use operand is the flag.
PowerPC "m" operands are represented as (flag, imm, reg) triples.
isRegTiedToDefOperand() would incorrectly interpret the imm as the flag.

llvm-svn: 76101
 2009-07-16 20:58:34 +00:00
Evan Cheng
981276bb16 Changed my mind. We now allow remat of instructions whose defs have subreg indices. 
llvm-svn: 76100
 2009-07-16 20:15:00 +00:00
Chris Lattner
aeeaf805c6 this should be xfailed on darwin. Darwin doesn't use the libstdc++ in the llvm-gcc distro, it uses the system version. 
llvm-svn: 76095
 2009-07-16 18:45:51 +00:00
Evan Cheng
39e5f6205a With recent MC changes, RIP base register is explicitly modeled. Make sure we add it when x86 V_SET0 / V_SETALLONES (by transforming it into a constpool load) into the use instruction. 
llvm-svn: 76094
 2009-07-16 18:44:05 +00:00
Dan Gohman
50e65d8c93 Fill in some holes in ScalarEvolution's loop iteration condition 
analysis. This allows indvars to emit a simpler loop trip count
expression.

llvm-svn: 76085
 2009-07-16 17:34:36 +00:00
Anton Korobeynikov
0d58ad2528 Make xfail proper 
llvm-svn: 76065
 2009-07-16 14:53:47 +00:00
Anton Korobeynikov
3e8bb65ec8 Temporary disable 16 bit bswap 
llvm-svn: 76063
 2009-07-16 14:35:57 +00:00
Anton Korobeynikov
e11a89ba74 Add bswap patterns 
llvm-svn: 76061
 2009-07-16 14:34:52 +00:00
Anton Korobeynikov
94f250ff30 Fix logic inversion for RI-mode address selection 
llvm-svn: 76052
 2009-07-16 14:31:14 +00:00
Anton Korobeynikov
4bba61182a Unbreak the test 
llvm-svn: 76051
 2009-07-16 14:30:49 +00:00
Anton Korobeynikov
373515d99e Expand 32-bit bitconverts via memory 
llvm-svn: 76050
 2009-07-16 14:30:29 +00:00
Anton Korobeynikov
080bdae588 Fix incomin arg stack frame offset in case we need to generate stack frame 
llvm-svn: 76049
 2009-07-16 14:29:57 +00:00
Anton Korobeynikov
2e8f54d16d Revert the commit, it just hides the real bug 
llvm-svn: 76045
 2009-07-16 14:28:26 +00:00
Anton Korobeynikov
bbf0fe2a76 Lower anyext to zext, 32-bit stuff does not have any implicit zero-extension side effects 
llvm-svn: 76035
 2009-07-16 14:24:41 +00:00
Anton Korobeynikov
3e670f38f9 Provide consistent subreg idx scheme. This (hopefully) fixes remaining divide problems 
llvm-svn: 76011
 2009-07-16 14:18:17 +00:00
Anton Korobeynikov
b3af53a626 Implement 'large' PIC model 
llvm-svn: 76006
 2009-07-16 14:16:05 +00:00
Anton Korobeynikov
2889a28adb Implement shifts properly (hopefilly - finally!) 
llvm-svn: 76005
 2009-07-16 14:15:24 +00:00
Anton Korobeynikov
f48e88136e Properly handle divides. As a bonus - implement memory versions of them. 
llvm-svn: 76003
 2009-07-16 14:14:33 +00:00
Anton Korobeynikov
e6b7c15a63 32 bit shifts have only 12 bit displacements 
llvm-svn: 76000
 2009-07-16 14:13:24 +00:00
Anton Korobeynikov
6c1091e7f3 Consolidate reg-imm / reg-reg-imm address mode selection logic in one place. 
llvm-svn: 75990
 2009-07-16 14:10:17 +00:00
Anton Korobeynikov
9a1ad49207 Add support for 12 bit displacements 
llvm-svn: 75988
 2009-07-16 14:09:35 +00:00