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Author SHA1 Message Date
Daniel Dunbar
918b0f7bd9 AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected 
to be matched.

llvm-svn: 104757
 2010-05-26 22:21:28 +00:00
Dan Gohman
2c70e05105 Reinstate checking of stackrestore, with checking for both Read 
and Write, and add a comment explaining this.

llvm-svn: 104756
 2010-05-26 22:21:25 +00:00
Jakob Stoklund Olesen
ee3ac9b299 Check that inherited subregisters all have a direct SubRegIndex. 
llvm-svn: 104755
 2010-05-26 22:15:07 +00:00
Jakob Stoklund Olesen
f0e15b4015 Give SubRegIndex names to all ARM subregisters. This will be required by 
TableGen shortly.

llvm-svn: 104754
 2010-05-26 22:15:03 +00:00
Dan Gohman
5ec2a338ac Stackrestore is not a load. 
llvm-svn: 104752
 2010-05-26 22:00:10 +00:00
Dan Gohman
bbac7ffe10 Fix a missing quote. 
llvm-svn: 104750
 2010-05-26 21:56:15 +00:00
Bill Wendling
a874b6d45a Add FIXME comment to remove this. 
llvm-svn: 104749
 2010-05-26 21:53:50 +00:00
Dan Gohman
35b59125b0 Remove a TODO which isn't practical. 
llvm-svn: 104748
 2010-05-26 21:50:41 +00:00
Daniel Dunbar
bf243d9440 MC: Add TargetMachine support for setting the value of MCRelaxAll with 
-filetype=obj.

llvm-svn: 104747
 2010-05-26 21:48:55 +00:00
Jakob Stoklund Olesen
1c0aa5f14a Add StringRef::compare_numeric and use it to sort TableGen register records. 
This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...

llvm-svn: 104745
 2010-05-26 21:47:28 +00:00
Dan Gohman
6b78ee79c1 Implement checking of the tail keyword. 
llvm-svn: 104744
 2010-05-26 21:46:36 +00:00
Jakob Stoklund Olesen
bf22a695bd Suppress emmission of empty subreg/superreg/alias sets. 
llvm-svn: 104741
 2010-05-26 21:35:55 +00:00
Devang Patel
2bbe13a797 There is no need to force an line number entry (using previous location) for a temp label at unknown location. 
llvm-svn: 104740
 2010-05-26 21:23:46 +00:00
Bill Wendling
49b19ff2c3 Add "setjmp_syscall", "savectx", "qsetjmp", "vfork", "getcontext" to the list of 
usual suspects that could "return twice".

llvm-svn: 104737
 2010-05-26 20:39:00 +00:00
Daniel Dunbar
c53aec29c9 MC: When running with -mc-relax-all, we can eagerly relax instructions and avoid creating unnecessary MCInstFragments. 
llvm-svn: 104736
 2010-05-26 20:37:03 +00:00
Daniel Dunbar
46774d4abc MC/Mach-O: Factor out EmitInstTo{Fragment,Data} for emitting MCInst's as MCInstFragments or appending onto an MCDataFragment. 
llvm-svn: 104735
 2010-05-26 20:37:00 +00:00
Jim Grosbach
bb4860d2a2 Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in 
ISD::. No functional change.

llvm-svn: 104734
 2010-05-26 20:22:18 +00:00
Devang Patel
2ea3f77515 Update debug info when live-in reg is copied into a vreg. 
llvm-svn: 104732
 2010-05-26 20:18:50 +00:00
Kevin Enderby
7eae1aeb51 Fix the x86 move to/from segment register instructions. 
llvm-svn: 104731
 2010-05-26 20:10:45 +00:00
Bill Wendling
fbe85886bb Move the check for "calls setjmp" to SelectionDAGISel so that it can be used by 
more than just the stack slot coloring algorithm.

llvm-svn: 104722
 2010-05-26 19:46:12 +00:00
Devang Patel
c24a269116 Identify instructions, that needs a label to mark debug info entity, in advance. This simplifies beginScope(). 
llvm-svn: 104720
 2010-05-26 19:37:24 +00:00
Dan Gohman
616845c384 Eliminate the use of PriorityQueue and just use a std::vector, 
implementing pop with a linear search for a "best" element. The priority
queue was a neat idea, but in practice the comparison functions depend
on dynamic information.

llvm-svn: 104718
 2010-05-26 18:52:00 +00:00
Dan Gohman
3391366b42 Fix indentation. 
llvm-svn: 104717
 2010-05-26 18:37:48 +00:00
Dan Gohman
a4a49b2108 Delete an unused function. 
llvm-svn: 104716
 2010-05-26 18:34:12 +00:00
Daniel Dunbar
1b8e1aafae MC: Change RelaxInstruction to only take the input and output instructions. 
llvm-svn: 104713
 2010-05-26 18:15:06 +00:00
Dan Gohman
ae6c721008 Fix a typo in a comment that Gabor noticed. 
llvm-svn: 104711
 2010-05-26 18:03:53 +00:00
Dale Johannesen
81afa3569a Testcase for 104624/104619/PR7191/8023512. 
Reduced from one provided by Duncan Sands, thanks!

llvm-svn: 104710
 2010-05-26 17:55:45 +00:00
Daniel Dunbar
7ab1807888 MC: Eliminate an unnecessary copy. 
llvm-svn: 104709
 2010-05-26 17:50:16 +00:00
Daniel Dunbar
77240e2337 MC: Simplify MayNeedRelaxation to not provide the fixups, so we can query it 
before encoding.

llvm-svn: 104707
 2010-05-26 17:45:29 +00:00
Devang Patel
6f08a37562 Remove dead code. 
llvm-svn: 104706
 2010-05-26 17:42:50 +00:00
Devang Patel
691615151f Do not construct location list backword! 
llvm-svn: 104705
 2010-05-26 17:29:32 +00:00
Jakob Stoklund Olesen
83d2cfd6cd Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104704
 2010-05-26 17:27:12 +00:00
Jim Grosbach
09ab258054 Add entry for llvm.eh.sjlj.longjmp. PR4999. 
llvm-svn: 104703
 2010-05-26 16:21:41 +00:00
Daniel Dunbar
87dcbd1ee5 MC: Eliminate MCAsmFixup, replace with MCFixup. 
llvm-svn: 104699
 2010-05-26 15:18:56 +00:00
Daniel Dunbar
fe22195ea6 MC: Simplify MCFixup and increase the available offset size. 
llvm-svn: 104698
 2010-05-26 15:18:40 +00:00
Daniel Dunbar
55c1bf55fe MC: Use accessors for access to MCAsmFixup. 
llvm-svn: 104697
 2010-05-26 15:18:31 +00:00
Daniel Dunbar
f50c283a31 MC: Change MCInst::dump_pretty to not include a trailing newline. 
llvm-svn: 104696
 2010-05-26 15:18:13 +00:00
Benjamin Kramer
40bf97c59d Kill unneeded SExt. 
llvm-svn: 104692
 2010-05-26 09:45:04 +00:00
Zhongxing Xu
2ae552a6c3 SRetReturnReg was set in LowerFormalArguments(). So only assert it here. 
llvm-svn: 104691
 2010-05-26 08:10:02 +00:00
Daniel Dunbar
a06aa279f4 MC: Eliminate MCFragment vtable, which was unnecessary. 
llvm-svn: 104689
 2010-05-26 06:50:57 +00:00
Shih-wei Liao
c535c0e055 Coding style change (Adding 1 missing space.) 
llvm-svn: 104670
 2010-05-26 04:46:50 +00:00
Shih-wei Liao
2f4221272a Adding the missing implementation for ARM::SBFX and ARM::UBFX. 
Fixing http://llvm.org/bugs/show_bug.cgi?id=7225.

llvm-svn: 104667
 2010-05-26 03:21:39 +00:00
Eric Christopher
13ac28ede3 Temporarily revert r104655 as it's breaking the bots. 
llvm-svn: 104664
 2010-05-26 01:59:55 +00:00
Jim Grosbach
95c228acb0 fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence. 
llvm-svn: 104661
 2010-05-26 01:22:21 +00:00
Jakob Stoklund Olesen
0fefdf4d2a Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism." 
This reverts commit 104654.

llvm-svn: 104660
 2010-05-26 01:21:14 +00:00
Dan Gohman
59cddd1327 Change push_all to a non-virtual function and implement it in the 
base class, since all the implementations are the same.

llvm-svn: 104659
 2010-05-26 01:10:55 +00:00
Dan Gohman
ba28c900a2 Delete an unused function. 
llvm-svn: 104658
 2010-05-26 00:56:27 +00:00
Dan Gohman
ff4bf1aacf Trim #include. 
llvm-svn: 104657
 2010-05-26 00:55:59 +00:00
Bill Wendling
04fbdac5ac Dale and Evan suggested putting the "check for setjmp" much earlier in the 
machine code generation. That's a good idea, so I made it so.

llvm-svn: 104655
 2010-05-26 00:32:40 +00:00
Jakob Stoklund Olesen
a2f0c34e41 Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104654
 2010-05-26 00:28:19 +00:00