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Author SHA1 Message Date
Evan Cheng
952943f744 Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. 
llvm-svn: 134590
 2011-07-07 03:55:05 +00:00
Bill Wendling
ba39846c2b Add a target hook to encode the compact unwind information. 
llvm-svn: 134577
 2011-07-07 00:54:13 +00:00
Jim Grosbach
eb31f6e012 Add isCodeGenOnly value to the CodeGenInstruction class. 
So users of a CGI don't have to look up the value directly from the original
Record; just like the rest of the convenience values in the class.

llvm-svn: 134576
 2011-07-07 00:48:02 +00:00
Lang Hames
2c2f6ed1f7 Added a testcase for PR10220. 
llvm-svn: 134573
 2011-07-07 00:36:02 +00:00
Devang Patel
a30ca05040 Add DEBUG messages. 
llvm-svn: 134572
 2011-07-07 00:14:27 +00:00
Evan Cheng
9581f645b3 Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC. 
llvm-svn: 134569
 2011-07-07 00:08:19 +00:00
Devang Patel
4011cc12b8 Use DBG_VALUE location while inserting DBG_VALUE during alloca promotion. 
llvm-svn: 134568
 2011-07-07 00:05:58 +00:00
Jakub Staszak
7f9c0d5ac8 Fix a bug in the "expect" intrinsic lowering. 
llvm-svn: 134566
 2011-07-06 23:50:16 +00:00
Eli Friedman
293141407b When tail-merging multiple blocks, make sure to correctly update the live-in list on the merged block to correctly account for the live-outs of all the predecessors. They might not be the same in all cases (the testcase I have involves a PHI node where one of the operands is an IMPLICIT_DEF). 
Unfortunately, the testcase I have is large and confidential, so I don't have a test to commit at the moment; I'll see if I can come up with something smaller where this issue reproduces.

<rdar://problem/9716278>

llvm-svn: 134565
 2011-07-06 23:41:48 +00:00
Jim Grosbach
b7ddd98a58 Typo. 
llvm-svn: 134563
 2011-07-06 23:38:13 +00:00
Devang Patel
94f4eec7e4 Remove dead code. 
llvm-svn: 134561
 2011-07-06 23:26:18 +00:00
Devang Patel
0abf331128 Typo. 
llvm-svn: 134559
 2011-07-06 23:09:51 +00:00
Bill Wendling
fd3f4e7040 Clean up the #includes. 
llvm-svn: 134557
 2011-07-06 22:52:32 +00:00
Eric Christopher
91acbb256c Grammar and 80-col. 
llvm-svn: 134555
 2011-07-06 22:41:18 +00:00
Owen Anderson
461ad5951b Fix a subtle issue in SmallVector. The following code did not work as expected: 
vec.insert(vec.begin(), vec[3]);
The issue was that vec[3] returns a reference into the vector, which is invalidated when insert() memmove's the elements down to make space.  The method needs to specifically detect and handle this case to correctly match std::vector's semantics.

Thanks to Howard Hinnant for clarifying the correct behavior, and explaining how std::vector solves this problem.

llvm-svn: 134554
 2011-07-06 22:36:59 +00:00
Devang Patel
47d505f9ef Handle cases where multiple dbg.declare and dbg.value intrinsics are tied to one alloca. 
llvm-svn: 134549
 2011-07-06 22:06:11 +00:00
Evan Cheng
5b5fb8c78b Add ARM MC registry routines. 
llvm-svn: 134547
 2011-07-06 22:02:34 +00:00
Evan Cheng
b0e0a318b7 Rename files for consistency. 
llvm-svn: 134546
 2011-07-06 22:01:53 +00:00
Nick Lewycky
233eabb210 Add ImmutableList::contains(). Patch by Rui Paulo! 
llvm-svn: 134545
 2011-07-06 21:59:48 +00:00
Jim Grosbach
9863be57e0 Mark ARM pseudo-instructions as isPseudo. 
This allows us to remove the (bogus and unneeded) encoding information from
the pseudo-instruction class definitions. All of the pseudos that haven't
been converted yet and still need encoding information instance from the normal
instruction classes and explicitly set isCodeGenOnly, and so are distinct
from this change.

llvm-svn: 134540
 2011-07-06 21:35:46 +00:00
Jim Grosbach
68759971b3 Don't require pseudo-instructions to carry encoding information. 
For now this is distinct from isCodeGenOnly, as code-gen-only
instructions can (and often do) still have encoding information
associated with them. Once we've migrated all of them over to true
pseudo-instructions that are lowered to real instructions prior to
the printer/emitter, we can remove isCodeGenOnly and just use isPseudo.

llvm-svn: 134539
 2011-07-06 21:33:38 +00:00
Devang Patel
214fa1739f Simplify. Consolidate dbg.declare handling in AllocaPromoter. 
llvm-svn: 134538
 2011-07-06 21:09:55 +00:00
Andrew Trick
f80318e090 indvars -disable-iv-rewrite: ExprToMap lives in Pass data, so be more 
careful about referencing values.

llvm-svn: 134537
 2011-07-06 21:07:10 +00:00
Jim Grosbach
99ece4392a Remove un-used encoding info from Pseudo MLAv5. 
Pseudo-instructions don't have encoding information, as they're lowered
to real instructions by the time we're doing binary encoding.

llvm-svn: 134533
 2011-07-06 20:57:35 +00:00
Eli Friedman
c3200e013c Fix missing triple support for RTEMS target. 
llvm-svn: 134532
 2011-07-06 20:56:26 +00:00
Andrew Trick
641b6e4222 indvars -disable-iv-rewrite: Added SimplifyCongruentIVs. 
llvm-svn: 134530
 2011-07-06 20:50:43 +00:00
Eli Friedman
4a5a5b1a0a Remove some unnecessary includes. 
llvm-svn: 134528
 2011-07-06 20:48:27 +00:00
Bill Wendling
479007f9af Constify getCompactUnwindRegNum. 
llvm-svn: 134527
 2011-07-06 20:33:48 +00:00
Evan Cheng
dcd3ea7062 createMCInstPrinter doesn't need TargetMachine anymore. 
llvm-svn: 134525
 2011-07-06 19:45:42 +00:00
Tobias Grosser
eda1c1a7ce LICM: Remove trailing white spaces 
llvm-svn: 134521
 2011-07-06 19:20:02 +00:00
Tobias Grosser
97b1ec50e3 LICM: Do not loose alignment on promotion 
The promotion code lost any alignment information, when hoisting loads and
stores out of the loop. This lead to incorrect aligned memory accesses. We now
use the largest alignment we can prove to be correct.

llvm-svn: 134520
 2011-07-06 19:19:55 +00:00
Jakub Staszak
4f5defff42 Add documenation about "branch_weight" metadata and __builtin_expect instruction 
llvm-svn: 134517
 2011-07-06 18:31:02 +00:00
Jakub Staszak
28bcc8673e Introduce "expect" intrinsic instructions. 
llvm-svn: 134516
 2011-07-06 18:22:43 +00:00
Kevin Enderby
43cb64711d Update MC/ELF/relocation.s with change to X86 PUSH64i8 in r134501. 
llvm-svn: 134511
 2011-07-06 17:55:20 +00:00
Kevin Enderby
59ba10f2ac Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a 
push with a small constant produces a 2-byte push.

llvm-svn: 134501
 2011-07-06 17:23:46 +00:00
David Greene
20bb374315 Allow tagless builds and fix debug build configuration. 
llvm-svn: 134498
 2011-07-06 16:54:14 +00:00
Evan Cheng
1112260be0 Remove the AsmWriterEmitter (unused) feature that rely on TargetSubtargetInfo. 
llvm-svn: 134457
 2011-07-06 02:02:33 +00:00
Dan Gohman
151e8ce446 Revert r134366 and add an explicit triple to make this test host-independent. 
llvm-svn: 134447
 2011-07-05 22:09:19 +00:00
Dan Gohman
7927fe2250 Remove the ObjC ARC passes from the default optimization list, and add 
extension points to be used by clang.

llvm-svn: 134444
 2011-07-05 22:01:44 +00:00
Devang Patel
bfd474b954 Preserve debug loc. 
llvm-svn: 134441
 2011-07-05 21:48:22 +00:00
Devang Patel
5f3ea5c3cb Speculatively revert r134431. 
llvm-svn: 134440
 2011-07-05 21:16:28 +00:00
Benjamin Kramer
b054fe79e3 Use memcmp. 
llvm-svn: 134439
 2011-07-05 20:28:00 +00:00
Rafael Espindola
9fdf25214f Really fix typo :-( 
llvm-svn: 134436
 2011-07-05 19:17:10 +00:00
Rafael Espindola
1b99dbcf82 Fix typo. 
llvm-svn: 134433
 2011-07-05 19:13:27 +00:00
Devang Patel
de1261583f Clear debug loc while updating insert point. 
llvm-svn: 134431
 2011-07-05 18:58:22 +00:00
Chad Rosier
bd4367f810 By default mkstemp() creates a temporary file with mode 0600, but the mode 
used for open is 0666.  Therefore, add the necessary permission bits for
consistency.
rdar://8621462

llvm-svn: 134430
 2011-07-05 18:55:31 +00:00
Jakob Stoklund Olesen
57f59c98ed Break infinite loop when the Hopfield network oscillates. 
This is impossible in theory, I can prove it. In practice, our near-zero
threshold can cause the network to oscillate between equally good
solutions.

<rdar://problem/9720596>

llvm-svn: 134428
 2011-07-05 18:46:42 +00:00
Rafael Espindola
e54f949f37 Compare all 4 bytes of the header. 
llvm-svn: 134427
 2011-07-05 18:41:47 +00:00
Eli Friedman
9765ae0015 Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269. 
llvm-svn: 134424
 2011-07-05 18:21:20 +00:00
Andrew Trick
8823fc0040 indvars -disable-iv-rewrite: avoid multiple IVs in weird cases. 
Putting back the helper that I removed on 7/1 to do this right.

llvm-svn: 134423
 2011-07-05 18:19:39 +00:00