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Commit Graph

73647 Commits

Author SHA1 Message Date
Jim Grosbach
0256b8b41f Use ARMPseudoExpand for BLr9, BLr9_pred, BXr9, and BXr9_pred.
TableGen'erated MC lowering pseudo-expansion.

llvm-svn: 134712
2011-07-08 18:15:12 +00:00
Evan Cheng
fb52c61529 Fix a dangling reference. Patch by Dave Abrahams. pr10311
llvm-svn: 134709
2011-07-08 18:04:22 +00:00
Devang Patel
91599d726c Refactor. It is inliner's responsibility to update line number information.
llvm-svn: 134708
2011-07-08 18:01:31 +00:00
Chandler Carruth
a8386a30b9 Add CMake support for the new TableGen file introduced in r134705.
llvm-svn: 134707
2011-07-08 17:54:08 +00:00
Jim Grosbach
5dd61ef1e9 Use TableGen'erated pseudo lowering for ARM.
Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.

More conversions to come.

llvm-svn: 134705
2011-07-08 17:40:42 +00:00
Jim Grosbach
290de9b4c9 TableGen'erated MC lowering for simple pseudo-instructions.
This allows the (many) pseudo-instructions we have that map onto a single
real instruction to have their expansion during MC lowering handled
automatically instead of the current cumbersome manual expansion required.
These sorts of pseudos are common when an instruction is used in situations
that require different MachineInstr flags (isTerminator, isBranch, et. al.)
than the generic instruction description has. For example, using a move
to the PC to implement a branch.

llvm-svn: 134704
2011-07-08 17:36:35 +00:00
Devang Patel
31505d2d78 Refactor.
llvm-svn: 134703
2011-07-08 17:09:57 +00:00
Devang Patel
756482ca98 Make provision to have floating point constants in .debug_loc expressions.
llvm-svn: 134702
2011-07-08 16:49:43 +00:00
Benjamin Kramer
560b1d3295 Apparently we can't expect a BinaryOperator here.
Should fix llvm-gcc selfhost.

llvm-svn: 134699
2011-07-08 12:08:24 +00:00
NAKAMURA Takumi
e737441fa8 cmake/modules/LLVMLibDeps.cmake: Update to appease cmake builds.
llvm-svn: 134696
2011-07-08 10:45:15 +00:00
Benjamin Kramer
44c76d239a Emit a more efficient magic number multiplication for exact sdivs.
We have to do this in DAGBuilder instead of DAGCombiner, because the exact bit is lost after building.

  struct foo { char x[24]; };
  long bar(struct foo *a, struct foo *b) { return a-b; }
is now compiled into
  movl	4(%esp), %eax
  subl	8(%esp), %eax
  sarl	$3, %eax
  imull	$-1431655765, %eax, %eax
instead of
  movl	4(%esp), %eax
  subl	8(%esp), %eax
  movl	$715827883, %ecx
  imull	%ecx
  movl	%edx, %eax
  shrl	$31, %eax
  sarl	$2, %edx
  addl	%eax, %edx
  movl	%edx, %eax

llvm-svn: 134695
2011-07-08 10:31:30 +00:00
Evan Cheng
50f2d8d304 Eliminate asm parser's dependency on TargetMachine:
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
  to generate asm matcher subtarget feature queries. e.g.
  "ModeThumb,FeatureThumb2" is translated to
  "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".

llvm-svn: 134678
2011-07-08 01:53:10 +00:00
Lang Hames
841a1fce67 Make GVN look through extractvalues for recognised intrinsics. GVN can then CSE ops that match values produced by the intrinsics.
llvm-svn: 134677
2011-07-08 01:50:54 +00:00
Akira Hatanaka
3249cd6612 Raise assertion when MachineOperand has unexpected target flag.
llvm-svn: 134671
2011-07-08 00:42:35 +00:00
Akira Hatanaka
a1dfe93665 Make sure variable Kind is assigned a value to suppress warning.
llvm-svn: 134668
2011-07-08 00:26:25 +00:00
Jakob Stoklund Olesen
99c67603c7 Fix more register allocation sensitive tests.
llvm-svn: 134667
2011-07-08 00:24:06 +00:00
Jakob Stoklund Olesen
47bc41b3c3 Remove a test that no longer makes sense.
It was testing a linear scan feature:

  Test if linearscan is unfavoring registers for allocation to allow
  more reuse of reloads from stack slots.

The greedy register allocator doesn't access any stack slots in this
function, so the linear scan feature was not being tested.

llvm-svn: 134666
2011-07-08 00:24:03 +00:00
Nick Lewycky
a82f7a687e Let the inline asm 'q' constraint match float, and on 64-bit double too.
Fixes PR9602!

llvm-svn: 134665
2011-07-08 00:19:27 +00:00
Eric Christopher
5fb023bb10 Go ahead and emit the barrier on x86-64 even without sse2. The
processor supports it just fine.

Fixes PR9675 and rdar://9740801

llvm-svn: 134664
2011-07-08 00:04:56 +00:00
Akira Hatanaka
90fcf55a54 Lower MachineInstr to MC Inst and print to .s files.
llvm-svn: 134661
2011-07-07 23:56:50 +00:00
Chandler Carruth
8f2e878dbf Fix CMake build's library dependencies.
llvm-svn: 134658
2011-07-07 23:45:45 +00:00
Eric Christopher
96527f39fd Handle fpcr register.
Part of PR10299 and rdar://9740322

llvm-svn: 134653
2011-07-07 22:54:12 +00:00
Eric Christopher
b7597bc669 Add support for the X86 'l' constraint.
Fixes PR10149 and rdar://9738585

llvm-svn: 134648
2011-07-07 22:29:07 +00:00
Eric Christopher
f3059adb4b Remove a FIXME. All of the standard ones are in the list.
llvm-svn: 134647
2011-07-07 22:29:03 +00:00
Akira Hatanaka
e3bcd9ec0a Remove unnecessary newline.
llvm-svn: 134645
2011-07-07 22:06:18 +00:00
Devang Patel
f97af90b4a Add DEBUG message.
llvm-svn: 134643
2011-07-07 21:44:42 +00:00
Evan Cheng
bbed81df25 Add Mode64Bit feature and sink it down to MC layer.
llvm-svn: 134641
2011-07-07 21:06:52 +00:00
Bill Wendling
49b8e85286 Move a function out-of-line.
llvm-svn: 134640
2011-07-07 21:05:13 +00:00
Akira Hatanaka
ccdaa7946c Rather than having printMemOperand change the way memory operands are printed
based on a modifier, split it into two functions.

llvm-svn: 134637
2011-07-07 20:54:20 +00:00
Akira Hatanaka
b4c145253b This patch adds a flag in MCAsmInfo that indicates whether dwarf register
numbers should be printed instead of symbolic register names in
MCAsmStreamer::EmitRegisterName. This is necessary because some versions of
GNU assembler won't accept code in which symbolic register names are used in
cfi directives. There is no change in behavior unless the flag is explicitly
set to true by a backend.

llvm-svn: 134635
2011-07-07 20:30:33 +00:00
Akira Hatanaka
9cddf51671 Define class MipsMCInstLower.
llvm-svn: 134633
2011-07-07 20:24:54 +00:00
Akira Hatanaka
382742199f Change visibility of MipsAsmPrinter.
llvm-svn: 134630
2011-07-07 20:10:52 +00:00
Akira Hatanaka
b5f9a0486c Define class MipsMCSymbolRefExpr.
llvm-svn: 134629
2011-07-07 19:27:22 +00:00
Akira Hatanaka
0de1fce485 Simplify MipsRegisterInfo::eliminateFrameIndex.
llvm-svn: 134628
2011-07-07 19:13:09 +00:00
Evan Cheng
dbc4dc612a Rewrite comment in English.
llvm-svn: 134627
2011-07-07 19:09:06 +00:00
Evan Cheng
faa59a86f1 Rename attribute 'thumb' to a more descriptive 'thumb-mode'.
llvm-svn: 134626
2011-07-07 19:05:12 +00:00
Akira Hatanaka
d3c031eb00 Reverse order of operands of address operand mem so that the base operand comes
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.

llvm-svn: 134625
2011-07-07 18:57:00 +00:00
Akira Hatanaka
31119a50bc Add missing return statement.
llvm-svn: 134622
2011-07-07 18:27:36 +00:00
Devang Patel
ff0a35a206 If known DebugLocs do not match then two DBG_VALUE machine instructions are not identical. For example,
DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:32:10 ]
        DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:31:10 ]

These two MIs represent identical value, 3.31...,  for one variable, ds, but they are not identical because the represent two separate instances of inlined variable "ds". 

llvm-svn: 134620
2011-07-07 17:45:33 +00:00
Joerg Sonnenberger
69f503e99c Recognize mipseb as alias for mips for symmetry with mipsel.
llvm-svn: 134617
2011-07-07 16:53:52 +00:00
Oscar Fuentes
835c073c59 Update CMake library dependencies
llvm-svn: 134616
2011-07-07 16:33:00 +00:00
Douglas Gregor
c21559842f Fix CMake build
llvm-svn: 134614
2011-07-07 15:59:22 +00:00
Cameron Zwarich
10c7a9fd7b The VMLA instruction and its friends are not actually fused; they're plain old
multiply-accumulate instructions with separate rounding steps.

llvm-svn: 134609
2011-07-07 08:28:52 +00:00
Evan Cheng
ac7afa4009 Sink feature IsThumb into MC layer.
llvm-svn: 134608
2011-07-07 08:26:46 +00:00
Evan Cheng
3f009eb37b Feature bits are 64-bits.
llvm-svn: 134607
2011-07-07 07:45:49 +00:00
Evan Cheng
18acf2200c Compute feature bits at time of MCSubtargetInfo initialization.
llvm-svn: 134606
2011-07-07 07:07:08 +00:00
Chris Lattner
fb02989d86 type can be null
llvm-svn: 134601
2011-07-07 05:29:18 +00:00
Chris Lattner
a52824b79e use a more efficient check for 'is metadata'
llvm-svn: 134599
2011-07-07 05:12:37 +00:00
Bill Wendling
2b47bfeaa9 Use ArrayRef instead of a std::vector&.
llvm-svn: 134595
2011-07-07 04:42:01 +00:00
Lang Hames
9e52663aa4 Add functions 'hasPredecessor' and 'hasPredecessorHelper' to SDNode. The
hasPredecessorHelper function allows predecessors to be cached to speed up
repeated invocations. This fixes PR10186.

X.isPredecessorOf(Y) now just calls Y.hasPredecessor(X)

Y.hasPredecessor(X) calls Y.hasPredecessorHelper(X, Visited, Worklist) with
empty Visited and Worklist sets (i.e. no caching over invocations).

Y.hasPredecessorHelper(X, Visited, Worklist) caches search state in Visited
and Worklist to speed up repeated calls. The Visited set is searched for X
before going to the worklist to further search the DAG if necessary.

llvm-svn: 134592
2011-07-07 04:31:51 +00:00