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504 Commits

Author SHA1 Message Date
Jim Grosbach
658b3efc30 ARM: Add missing two-operand VBIC aliases. 
llvm-svn: 156019
 2012-05-02 21:11:56 +00:00
Lang Hames
7d83af4ed0 Fix the order of the operands in the llvm.fma intrinsic patterns for ARM, 
<rdar://problem/11325085>.

llvm-svn: 155724
 2012-04-27 18:51:24 +00:00
Tim Northover
876c151146 Use VLD1 in NEON extenting-load patterns instead of VLDR. 
On some cores it's a bad idea for performance to mix VFP and NEON instructions
and since these patterns are NEON anyway, the NEON load should be used.

llvm-svn: 155630
 2012-04-26 08:46:29 +00:00
Jim Grosbach
66edf44403 Tidy up. 80 columns, whitespace, et. al. 
llvm-svn: 155399
 2012-04-23 22:04:10 +00:00
Jim Grosbach
4221412829 ARM: VSLI two-operand assmebly aliases are tblgen'erated. 
llvm-svn: 155393
 2012-04-23 21:22:04 +00:00
Jim Grosbach
8aac7f6a7c ARM: tblgen'erate VSRA/VRSRA/VSRI assembly two-operand aliases. 
llvm-svn: 155392
 2012-04-23 21:00:49 +00:00
Jim Grosbach
d377bc4e77 ARM: vqdmulh two-operand aliases are tblgen'erated now. 
llvm-svn: 155387
 2012-04-23 20:37:20 +00:00
Jim Grosbach
ba84724346 ARM: tblgen'erate more NEON two-operand aliases. 
VMUL and VEXT.

llvm-svn: 155258
 2012-04-20 23:46:33 +00:00
Jim Grosbach
5329904457 ARM: tblgen'erate more NEON two-operand aliases. 
llvm-svn: 155254
 2012-04-20 23:30:14 +00:00
Jim Grosbach
e33d0c7063 ARM: Update NEON assembly two-operand aliases. 
Use the new TwoOperandAliasConstraint to handle lots of the two-operand aliases
for NEON instructions. There's still more to go, but this is a good chunk of
them.

llvm-svn: 155210
 2012-04-20 18:12:54 +00:00
James Molloy
44927f5296 Fix bad EXTRACT_SUBREG in instruction selection for extending-loads on NEON. 
llvm-svn: 154915
 2012-04-17 08:18:00 +00:00
Jim Grosbach
13a45d88e5 ARM two-operand forms for vhadd and vhsub instructions. 
rdar://11252521

llvm-svn: 154875
 2012-04-16 23:00:25 +00:00
Jim Grosbach
b6c95c9f42 ARM assembly two-operand forms for VRSHL. 
rdar://11252521

llvm-svn: 154840
 2012-04-16 18:03:16 +00:00
Jim Grosbach
d961988871 ARM two-operand aliases for VRHADD instructions. 
rdar://11252521

llvm-svn: 154832
 2012-04-16 17:14:11 +00:00
Jim Grosbach
86b5cd7421 ARM 'vuzp.32 Dd, Dm' is a pseudo-instruction. 
While there is an encoding for it in VUZP, the result of that is undefined,
so we should avoid it. Define the instruction as a pseudo for VTRN.32
instead, as the ARM ARM indicates.

rdar://11222366

llvm-svn: 154511
 2012-04-11 17:40:18 +00:00
Jim Grosbach
e54b48cd74 ARM 'vzip.32 Dd, Dm' is a pseudo-instruction. 
While there is an encoding for it in VZIP, the result of that is undefined,
so we should avoid it. Define the instruction as a pseudo for VTRN.32
instead, as the ARM ARM indicates.

rdar://11221911

llvm-svn: 154505
 2012-04-11 16:53:25 +00:00
Evan Cheng
f138fb4599 Add more fused mul+add/sub patterns. rdar://10139676 
llvm-svn: 154484
 2012-04-11 06:59:47 +00:00
Evan Cheng
f9baff015d Clean up ARM fused multiply + add/sub support some more: rename some isel 
predicates.
Also remove NEON2 since it's not really useful and it is confusing. If
NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it
really mean?

rdar://10139676

llvm-svn: 154480
 2012-04-11 05:33:07 +00:00
Evan Cheng
12bfe1150d Fix a number of problems with ARM fused multiply add/subtract instructions. 
1. The new instruction itinerary entries are not properly described.
2. The asm parser can't handle vfms and vfnms.
3. There were no assembler, disassembler test cases.
4. HasNEON2 has the wrong assembler predicate.
rdar://10139676

llvm-svn: 154456
 2012-04-11 00:13:00 +00:00
Evan Cheng
f9617f7f54 Handle llvm.fma.* intrinsics. rdar://10914096 
llvm-svn: 154439
 2012-04-10 21:40:28 +00:00
Jim Grosbach
5d11d38750 ARM assembly aliases for two-operand V[R]SHR instructions. 
rdar://11189467

llvm-svn: 154087
 2012-04-05 07:23:53 +00:00
Jim Grosbach
92ee2a8454 ARM encoding for VSWP got the second operand incorrect. 
Make the non-tied register operand names line up with what the base
class encoding handler expects.

rdar://11157236

llvm-svn: 153766
 2012-03-30 18:53:01 +00:00
Jakob Stoklund Olesen
7623979dd6 Spill DPair registers, not just QPR. 
The arm_neon intrinsics can create virtual registers from the DPair
register class which allows both even-odd and odd-even D-register pairs.

This fixes PR12389.

llvm-svn: 153603
 2012-03-28 21:20:32 +00:00
Richard Barton
201661d4bc Fixup VST1.32 with writeback instruction. Also re-factor non-writeback version. 
llvm-svn: 153573
 2012-03-28 10:18:11 +00:00
Jim Grosbach
3b5f99f716 ARM more NEON VLD/VST composite physical register refactoring. 
Register pair, all lanes subscripting.

llvm-svn: 152157
 2012-03-06 23:10:38 +00:00
Jim Grosbach
a3eeee8a91 ARM refactor more NEON VLD/VST instructions to use composite physregs 
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.

llvm-svn: 152150
 2012-03-06 22:01:44 +00:00
Jim Grosbach
a6b09b4691 ARM Refactor VLD/VST spaced pair instructions. 
Use the new composite physical registers.

llvm-svn: 152063
 2012-03-05 21:43:40 +00:00
Jim Grosbach
d0fb2e7c99 ARM Remove a bit of dead code. 
llvm-svn: 152061
 2012-03-05 21:09:58 +00:00
Jim Grosbach
fdfaed95ae ARM refactor away a bunch of VLD/VST pseudo instructions. 
With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.

llvm-svn: 152045
 2012-03-05 19:33:30 +00:00
Sebastian Pop
e6eeed8151 updated patch for the ARM fused multiply add/sub 
In this update:
- I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2.
- I kept setting .fpu=neon-vfpv4 code attribute because that is what the
assembler understands.

Patch by Ana Pazos <apazos@codeaurora.org>

llvm-svn: 152036
 2012-03-05 17:39:52 +00:00
Jim Grosbach
329e745b30 ARM vbit/vbif/vbsl assembly optional size suffix. 
These instructions accept but do not require a size suffix.

rdar://10947225

llvm-svn: 151646
 2012-02-28 19:11:07 +00:00
James Molloy
6cbdd131b3 Improve generated code for extending loads and some trunc stores on ARM. 
Teach TargetSelectionDAG about lengthening loads for vector types and set v4i8 as legal. Allow FP_TO_UINT for v4i16 from v4i32.

llvm-svn: 150956
 2012-02-20 09:24:05 +00:00
Jia Liu
b077b6085d Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Lang Hames
a486c1b72e Third time's the charm...? 
llvm-svn: 150447
 2012-02-14 00:34:30 +00:00
Lang Hames
a20e2c80fd Unswap swap operands, partially reducing confusion. 
llvm-svn: 150444
 2012-02-14 00:17:12 +00:00
Lang Hames
fab0ff3380 Make operands for VSWP read-modify-write. 
llvm-svn: 150433
 2012-02-13 23:37:19 +00:00
Jim Grosbach
e8095f3b49 NEON VLD4(all lanes) assembly parsing and encoding. 
llvm-svn: 148884
 2012-01-25 00:01:08 +00:00
Jim Grosbach
9c21d45c29 Tidy up. Rename VLD4DUP patterns for consistency. 
llvm-svn: 148883
 2012-01-24 23:47:07 +00:00
Jim Grosbach
f478b2a706 NEON VLD3(all lanes) assembly parsing and encoding. 
llvm-svn: 148882
 2012-01-24 23:47:04 +00:00
Jim Grosbach
e151b15949 NEON VST4(one lane) assembly parsing and encoding. 
llvm-svn: 148836
 2012-01-24 18:53:13 +00:00
Jim Grosbach
a78348fcda NEON VLD4(one lane) assembly parsing and encoding. 
llvm-svn: 148832
 2012-01-24 18:37:25 +00:00
Jim Grosbach
f3607eac5d NEON Two-operand assembly aliases for VSRA. 
llvm-svn: 148821
 2012-01-24 17:55:36 +00:00
Jim Grosbach
630dd380c7 NEON Two-operand assembly aliases for VSLI. 
llvm-svn: 148819
 2012-01-24 17:49:15 +00:00
Jim Grosbach
42c0f99aa0 NEON Two-operand assembly aliases for VSRI. 
llvm-svn: 148818
 2012-01-24 17:46:58 +00:00
Jim Grosbach
e00b69bf5b NEON add correct predicates for some asm aliases. 
llvm-svn: 148815
 2012-01-24 17:23:29 +00:00
Jim Grosbach
3be662b372 NEON VST4(multiple 4 element structures) assembly parsing. 
llvm-svn: 148764
 2012-01-24 00:58:13 +00:00
Jim Grosbach
ca32a49eb5 NEON VLD4(multiple 4 element structures) assembly parsing. 
llvm-svn: 148762
 2012-01-24 00:43:17 +00:00
Jim Grosbach
522c9aefea Fix typo. 
llvm-svn: 148757
 2012-01-24 00:12:39 +00:00
Jim Grosbach
a4687dcf5a NEON VST3(single element from one lane) assembly parsing. 
llvm-svn: 148755
 2012-01-24 00:07:41 +00:00
Jim Grosbach
048162ddf9 NEON VST3(multiple 3-element structures) assembly parsing. 
llvm-svn: 148748
 2012-01-23 23:45:44 +00:00