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Author SHA1 Message Date
Bob Wilson
3e4aa8ec69 Add a Neon intrinsic test generator. 
This is still a WIP.  It's already good enough to expose a few bugs, though.

llvm-svn: 121868
 2010-12-15 16:58:45 +00:00
Bob Wilson
114df2f88a Fix Neon intrinsic immediate range checking for some double-register operands. 
Some quad-register intrinsics with lane operands only take a double-register
operand for the vector containing the lane.  The valid range of lane numbers
is then half as big as you would expect from the quad-register type.
Note: This currently has no effect because those intrinsics are now handled
entirely in the header file using __builtin_shufflevector, which does its own
range checking, but I want to use this for generating tests.

llvm-svn: 121867
 2010-12-15 16:58:42 +00:00
Duncan Sands
2699fb1072 Move Sub simplifications and additional Add simplifications out of 
instcombine and into InstructionSimplify.

llvm-svn: 121861
 2010-12-15 14:07:39 +00:00
Duncan Sands
a9b837f7c7 If we detect that the instruction we are simplifying is unreachable, arrange for 
it to be replaced by undef rather than not replaced at all, the idea being that
this may reduce the amount of work done by whoever called InstructionSimplify.

llvm-svn: 121860
 2010-12-15 11:02:22 +00:00
Frits van Bommel
83b7c3773f Teach jump threading to "look through" a select when the branch direction of a terminator depends on it. 
When it sees a promising select it now tries to figure out whether the condition of the select is known in any of the predecessors and if so it maps the operands appropriately.

llvm-svn: 121859
 2010-12-15 09:51:20 +00:00
Bill Wendling
ab9df10ee5 Add fixups for Thumb LDR/STR instructions. 
llvm-svn: 121858
 2010-12-15 08:51:02 +00:00
Rafael Espindola
94d026d157 Relax alignment fragments. 
With this we don't need the EffectiveSize field anymore. Without that field
LayoutFragment only updates offsets and we don't need to invalidate the
current fragment when it is relaxed (only the ones following it).

This is also a very small improvement in the accuracy of the layout info as
we now use the after relaxation size immediately.

llvm-svn: 121857
 2010-12-15 08:45:53 +00:00
Rafael Espindola
f55f520a7a Patch by David Meyer to avoid a O(N^2) behaviour when relaxing fragments. 
Since we now don't update addresses so early, we might relax a bit more than
we need to. This is simillar to the issue in PR8467.

llvm-svn: 121856
 2010-12-15 07:39:29 +00:00
Chris Lattner
63d08e3444 add another overflow idiom 
llvm-svn: 121854
 2010-12-15 07:28:58 +00:00
Chris Lattner
ec899c30d9 add a note about overflow idiom recognition. 
llvm-svn: 121853
 2010-12-15 07:25:55 +00:00
Rafael Espindola
102a0b7b74 Generalize an assert. 
llvm-svn: 121851
 2010-12-15 07:12:24 +00:00
Chris Lattner
82b8cda077 add a shift/imul missed optimization 
llvm-svn: 121850
 2010-12-15 07:10:43 +00:00
Chris Lattner
d2022fee87 add a note about a SPEC hack that gcc mainline does. 
llvm-svn: 121849
 2010-12-15 06:38:24 +00:00
Chris Lattner
81815cd4db take care of some todos, transforming [us]mul_lohi into 
a wider mul if the wider mul is legal.

llvm-svn: 121848
 2010-12-15 06:04:19 +00:00
Chris Lattner
3bec2e7d0d merge two tests 
llvm-svn: 121847
 2010-12-15 05:58:59 +00:00
Chris Lattner
746d6a1f60 when transforming a MULHS into a wider MUL, there is no need to SRA the 
result, the top bits are truncated off anyway, just use SRL.

llvm-svn: 121846
 2010-12-15 05:51:39 +00:00
Chris Lattner
1499119975 make qsort predicate more conformant by returning 0 for equal values. 
llvm-svn: 121838
 2010-12-15 04:52:41 +00:00
Chris Lattner
e1ee3c537d various cleanups to tblgen, patch by Garrison Venn! 
llvm-svn: 121837
 2010-12-15 04:48:22 +00:00
Bill Wendling
0611f0ab0b Add mention that we support FreeBSD/amd64. 
llvm-svn: 121832
 2010-12-15 01:35:55 +00:00
Kevin Enderby
6b3ae489f8 Add some more MC tests for ARM arithmetic instructions that update or don't 
update the condition codes.  These come from my test generator and are just
the ones that MC currently assembles correctly.

llvm-svn: 121830
 2010-12-15 01:24:36 +00:00
Mikhail Glushenkov
7734f4702c Copy-pastos. 
llvm-svn: 121829
 2010-12-15 01:22:34 +00:00
Mikhail Glushenkov
a1dff84381 Remove ConvertToMAttrImpl, it became too '-march'-specific. 
llvm-svn: 121828
 2010-12-15 01:22:29 +00:00
Mikhail Glushenkov
85f1ed369c llvmc: Support -march arguments that should be forwarded to llc as -mcpu. 
llvm-svn: 121827
 2010-12-15 01:22:25 +00:00
Mikhail Glushenkov
8cf4959bf1 llvmc: Better -mfpu/-mcpu support for ARM & PPC. 
llvm-svn: 121826
 2010-12-15 01:22:20 +00:00
Mikhail Glushenkov
cc4f5dc841 llvmc: more complete -march table for ARM. 
llvm-svn: 121825
 2010-12-15 01:22:15 +00:00
Mikhail Glushenkov
62c42888bd llvmc: Support -mabi/-mfloat-abi. 
llvm-svn: 121824
 2010-12-15 01:22:10 +00:00
Mikhail Glushenkov
04ca263355 llvmc: Forward -march/-mcpu/-mtune to as & ld. 
llvm-svn: 121823
 2010-12-15 01:22:05 +00:00
Mikhail Glushenkov
2e471b81da llvmc: make switch options ZeroOrMore by default. 
llvm-svn: 121822
 2010-12-15 01:21:59 +00:00
Bill Wendling
258739db7e Reapply r121808 now that the missing patterns have been supplied. 
llvm-svn: 121820
 2010-12-15 01:03:19 +00:00
Bill Wendling
2764f25c78 Add some missing patterns now that tLDRB and tLDRH are split into reg and 
immediate versions.

llvm-svn: 121819
 2010-12-15 00:58:57 +00:00
Owen Anderson
de42e1136e Fix PR8790, another instance where unreachable code can cause instruction simplification to fail, 
this case involve a select that simplifies to itself.

llvm-svn: 121817
 2010-12-15 00:55:35 +00:00
Owen Anderson
df08ec80df Cleanup trailing whitespace. 
llvm-svn: 121816
 2010-12-15 00:52:44 +00:00
Bill Wendling
ad13b53237 Revert r121808 until I can fix the build. 
llvm-svn: 121815
 2010-12-15 00:04:00 +00:00
Jim Grosbach
386d8fc22c thumb adr fixup needs alignment just like the t2 version. 
llvm-svn: 121812
 2010-12-14 23:47:35 +00:00
Bill Wendling
ab3d22ba7f Comments and cleaning. 
llvm-svn: 121809
 2010-12-14 23:42:48 +00:00
Bill Wendling
2883bbb8c0 Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. In 
particular, we want

   ldr r2, [r3]

to be equivalent to

   ldr r2, [r3, #0]

and not

   ldr r2, [r3, r0]

llvm-svn: 121808
 2010-12-14 23:40:49 +00:00
Jakob Stoklund Olesen
48800c9689 Simplify RegAllocGreedy's use of register aliases. 
llvm-svn: 121807
 2010-12-14 23:38:19 +00:00
Jakob Stoklund Olesen
7ee6f83da1 Simplify CCState's use of register aliases. 
llvm-svn: 121806
 2010-12-14 23:28:01 +00:00
Jakob Stoklund Olesen
03856151db Simplify AggressiveAntiDepBreaker's use of register aliases. 
llvm-svn: 121805
 2010-12-14 23:23:15 +00:00
Jakob Stoklund Olesen
870fbdd686 Simplyfy RegAllocBasic by using getOverlaps instead of getAliasSet. 
llvm-svn: 121801
 2010-12-14 23:10:48 +00:00
Jakob Stoklund Olesen
22ff831572 Introduce TargetRegisterInfo::getOverlaps(Reg), returning a list of all 
registers that alias Reg, including itself. This is almost the same as the
existing getAliasSet() method, except for the inclusion of Reg.

The name matches the reflexive TRI::regsOverlap(x, y) relation.

It is very common to do stuff to a register and all its aliases:

  stuff(Reg)
  for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias)
    stuff(*Alias);

That can now be written as the simpler:

  for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias)
    stuff(*Alias);

This change requires a bit more constant space for the alias lists because Reg
is included and because the empty alias list cannot be shared any longer.

If the getAliasSet method is eventually removed, this space can be reclaimed by
sharing overlap lists. For instance, %rax and %eax have identical overlap sets.

llvm-svn: 121800
 2010-12-14 23:03:42 +00:00
Jim Grosbach
1e943cc60d Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755 
llvm-svn: 121798
 2010-12-14 22:28:03 +00:00
Bill Wendling
213a3d080d Fix comment. 
llvm-svn: 121797
 2010-12-14 22:26:49 +00:00
Bill Wendling
7e589d4753 Multiclassify the LDR/STR encoding patterns. The only functionality difference 
is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.

llvm-svn: 121794
 2010-12-14 22:10:49 +00:00
Evan Cheng
7e96e67d98 Fix a minor bug in two-address pass. It was missing a commute opportunity. 
regB = move RCX
regA = op regB, regC
RAX  = move regA
where both regB and regC are killed. If regB is constrainted to non-compatible
physical registers but regC is not constrainted at all, then it's better to
commute the instruction.
       movl    %edi, %eax
       shlq    $32, %rcx
       leaq    (%rcx,%rax), %rax
=>
       movl    %edi, %eax
       shlq    $32, %rcx
       orq     %rcx, %rax
rdar://8762995

llvm-svn: 121793
 2010-12-14 21:34:53 +00:00
Jim Grosbach
70721628b4 trailing whitespace 
llvm-svn: 121792
 2010-12-14 21:28:29 +00:00
Matt Beaumont-Gay
01264443a8 Move debugging code entirely within DEBUG(). Silences an unused variable 
warning in the opt build.

llvm-svn: 121791
 2010-12-14 21:14:55 +00:00
Jim Grosbach
e84e95e6d2 Refactor a bit for legibility. 
llvm-svn: 121790
 2010-12-14 21:10:47 +00:00
Jim Grosbach
ef58d5968e trailing whitespace. 
llvm-svn: 121789
 2010-12-14 20:46:39 +00:00
Jim Grosbach
13d82ea2b1 Make sure to propagate the predicate operands for LEApcrel to ADR. 
llvm-svn: 121788
 2010-12-14 20:45:47 +00:00