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be996a5261
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78 Commits

Author SHA1 Message Date
Richard Osborne
be996a5261 [XCore] Add missing 0r instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173623
 2013-01-27 20:42:57 +00:00
Richard Osborne
32d4ba5aeb Add instruction encodings / disassembly support for l4r instructions. 
llvm-svn: 173501
 2013-01-25 21:55:32 +00:00
Richard Osborne
065cd10bb5 Use the correct format in the STW / SETPSC instruction names. 
llvm-svn: 173494
 2013-01-25 21:25:12 +00:00
Richard Osborne
e119783a82 Fix order of operands for crc8_l4r 
The order in which operands appear in the encoded instruction is different
to order in which they appear in assembly. This changes the XCore backend to
use the instruction encoding order.

llvm-svn: 173493
 2013-01-25 21:20:28 +00:00
Richard Osborne
4269c34e3d Add instruction encodings / disassembly support for l5r instructions. 
llvm-svn: 173479
 2013-01-25 20:20:07 +00:00
Richard Osborne
73533fb821 Fix order of operands for l5r instructions. 
With this change the operands order matches the order in which the operands
are encoded in the instruction.

llvm-svn: 173477
 2013-01-25 20:16:00 +00:00
Richard Osborne
bc9a485488 Use correct mnemonic / instruction name for ldivu. 
llvm-svn: 173476
 2013-01-25 20:11:26 +00:00
Richard Osborne
8f90349114 Add instruction encodings / disassembly support for l6r instructions. 
llvm-svn: 173288
 2013-01-23 20:08:11 +00:00
Richard Osborne
6453bd631a Add instruction encodings / disassembly support for u10 / lu10 instructions. 
llvm-svn: 173204
 2013-01-22 22:55:04 +00:00
Richard Osborne
9599bb34e9 Fix some incorrectly named u10 / lu10 instructions. 
llvm-svn: 173090
 2013-01-21 21:12:30 +00:00
Richard Osborne
fe2c8cca9d Remove unused multiclass. 
llvm-svn: 173087
 2013-01-21 20:50:54 +00:00
Richard Osborne
02e7d3f377 Add instruction encodings / disassembly support for u6 / lu6 instructions. 
llvm-svn: 173086
 2013-01-21 20:44:17 +00:00
Richard Osborne
0b3c4f3112 Add instruction encoding / disassembly support for ru6 / lru6 instructions. 
llvm-svn: 173085
 2013-01-21 20:42:16 +00:00
Richard Osborne
b46d4f8f86 Use correct format for the LDAWCP instruction (u6). 
llvm-svn: 173083
 2013-01-21 20:32:54 +00:00
Richard Osborne
c048ec5160 Add instruction encodings / disassembly support for l2rus instructions. 
llvm-svn: 172987
 2013-01-20 18:51:15 +00:00
Richard Osborne
5688672b0b Add instruction encodings / disassembly support for l3r instructions. 
llvm-svn: 172986
 2013-01-20 18:37:49 +00:00
Richard Osborne
400fb5329e Add instruction encodings / disassembler support for 2rus instructions. 
llvm-svn: 172985
 2013-01-20 17:22:43 +00:00
Richard Osborne
3a5e1fcceb Add instruction encodings / disassembly support 3r instructions. 
It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.

llvm-svn: 172984
 2013-01-20 17:18:47 +00:00
Richard Osborne
efed5dbcc7 Add instruction encodings / disassembly support for l2r instructions. 
llvm-svn: 170345
 2012-12-17 16:28:02 +00:00
Richard Osborne
b4aaa991f6 Add instruction encodings for PEEK and ENDIN. 
Previously these were marked with the wrong format.

llvm-svn: 170334
 2012-12-17 14:23:54 +00:00
Richard Osborne
c66ab02537 Add instruction encodings / disassembly support for rus instructions. 
llvm-svn: 170330
 2012-12-17 13:50:04 +00:00
Richard Osborne
92f0d25122 Add instruction encodings for ZEXT and SEXT. 
Previously these were marked with the wrong format.

llvm-svn: 170327
 2012-12-17 13:20:37 +00:00
Richard Osborne
cccafe2726 Add instruction encodings / disassembly support for 2r instructions. 
llvm-svn: 170323
 2012-12-17 12:29:31 +00:00
Richard Osborne
815fca9724 Add instruction encodings / disassembly support for 0r instructions. 
llvm-svn: 170322
 2012-12-17 12:26:29 +00:00
Richard Osborne
5c2cbafeba Add instruction encodings and disassembly for 1r instructions. 
llvm-svn: 170293
 2012-12-16 17:37:34 +00:00
Richard Osborne
514735415d Replace ${:comment} with the comment symbol. 
llvm-svn: 170286
 2012-12-16 15:59:02 +00:00
Jakob Stoklund Olesen
02cb24658a Fix load/store SDNode flags. 
llvm-svn: 162558
 2012-08-24 14:43:30 +00:00
Bill Wendling
17b12b72bc Remove tabs. 
llvm-svn: 160477
 2012-07-19 00:11:40 +00:00
Jakob Stoklund Olesen
b8af245a15 Remove variable_ops from call instructions in most targets. 
Call instructions are no longer required to be variadic, and
variable_ops should only be used for instructions that encode a variable
number of arguments, like the ARM stm/ldm instructions.

llvm-svn: 160189
 2012-07-13 20:44:29 +00:00
Richard Osborne
96c0be7351 Fix pattern for MKMSK instruction. 
llvm-svn: 158409
 2012-06-13 17:59:12 +00:00
Jia Liu
b077b6085d Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Richard Osborne
0ec86a885b Fix 80 column violations. 
Original patch by Liu.

llvm-svn: 140385
 2011-09-23 16:28:10 +00:00
Richard Osborne
05cda7958d Mark LDWCP as having no side effects. 
llvm-svn: 139494
 2011-09-12 14:41:31 +00:00
Richard Osborne
6b6b0b535d Add Uses=[SP] to call instructions. This fixes a miscompilation with a 
variable sized alloca.

llvm-svn: 138433
 2011-08-24 13:32:43 +00:00
Richard Osborne
415c5ff412 Add intrinsics for SETEV, GETED, GETET. 
llvm-svn: 137938
 2011-08-18 13:00:48 +00:00
Richard Osborne
b469141419 Add intrinsics for the zext / sext instructions. 
llvm-svn: 135476
 2011-07-19 13:28:50 +00:00
Richard Osborne
50303e0d38 Add intrinsics for the testct, testwct instructions. 
llvm-svn: 135475
 2011-07-19 13:00:40 +00:00
Richard Osborne
409c0d7768 Add intrinsics for the peek and endin instructions. 
llvm-svn: 135474
 2011-07-19 12:50:25 +00:00
Richard Osborne
660fe84614 Fix 80 column violations. 
llvm-svn: 132341
 2011-05-31 16:30:33 +00:00
Richard Osborne
4293c93896 Add XCore intrinsic for crc8. 
llvm-svn: 132340
 2011-05-31 16:24:49 +00:00
Richard Osborne
34a4652dcd Add XCore intrinsic for crc32. 
llvm-svn: 132336
 2011-05-31 14:47:36 +00:00
Richard Osborne
5b9df0d075 Add XCore intrinsics for initializing / starting / synchronizing threads. 
llvm-svn: 128633
 2011-03-31 15:13:13 +00:00
Richard Osborne
6bad79b514 Add XCore intrinsic for setpsc. 
llvm-svn: 127821
 2011-03-17 18:42:05 +00:00
Richard Osborne
8b90369d96 Add XCore intrinsics for setclk, setrdy. 
llvm-svn: 127761
 2011-03-16 21:56:00 +00:00
Richard Osborne
318e25c620 Add checkevent intrinsic to check if any resources owned by the current thread 
can event.

llvm-svn: 127741
 2011-03-16 18:34:00 +00:00
Richard Osborne
70204c1c29 Add XCore intrinsics for getps, setps, setsr and clrsr. 
llvm-svn: 127678
 2011-03-15 13:45:47 +00:00
Richard Osborne
a8df984a31 Add XCore intrinsic for eeu instruction. 
llvm-svn: 126384
 2011-02-24 13:39:18 +00:00
Richard Osborne
d9564589f6 Add XCore intrinsic for clre instruction. 
llvm-svn: 126322
 2011-02-23 18:52:05 +00:00
Richard Osborne
4a55817288 Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable 
events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.

llvm-svn: 126320
 2011-02-23 18:35:59 +00:00
Richard Osborne
aaac1b01fd Add XCore intrinsic for the setv instruction. 
llvm-svn: 126315
 2011-02-23 16:46:37 +00:00