Stepan Dyatkovskiy
bf1423bdcd
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11.
...
llvm-svn: 146341
2011-12-11 14:35:48 +00:00
Chad Rosier
fa74c25947
Revert associate SelectInsertValue test as well.
...
llvm-svn: 146332
2011-12-10 21:34:28 +00:00
Chad Rosier
d8a265c838
Revert r146322 to appease buildbots. Original commit message:
...
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for
FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second
attempt.
llvm-svn: 146328
2011-12-10 19:55:03 +00:00
Stepan Dyatkovskiy
5b2b42e8c9
Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt.
...
llvm-svn: 146322
2011-12-10 08:42:24 +00:00
Eli Friedman
ca06c3a2bd
Splats can contain undef's; make sure to handle them correctly. PR11526.
...
llvm-svn: 146299
2011-12-09 23:54:42 +00:00
Chad Rosier
7e0dc23863
[fast-isel] Add support for selecting insertvalue.
...
rdar://10530851
llvm-svn: 146276
2011-12-09 20:09:54 +00:00
Daniel Dunbar
c192ce505d
Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsics
...
sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP,
FEXP2).", it is failing tests.
llvm-svn: 146157
2011-12-08 17:32:18 +00:00
Stepan Dyatkovskiy
8fde5b6eb4
Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).
...
llvm-svn: 146143
2011-12-08 07:55:03 +00:00
Chad Rosier
70dd1f98af
[arm-fast-isel] Doublewords only require word-alignment.
...
rdar://10528060
llvm-svn: 145891
2011-12-06 01:44:17 +00:00
Jakob Stoklund Olesen
af85f53dd0
Align ARM constant pool islands via their basic block.
...
Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired
alignment of 4 bytes emitted by ARMAsmPrinter. Now the same alignment
is set on the basic block.
This is in preparation of supporting ARM constant pool islands with
different alignments.
llvm-svn: 145890
2011-12-06 01:43:02 +00:00
Anton Korobeynikov
e2277de6a7
Emit the ctors in the proper order on ARM/EABI.
...
Maybe some targets should use this as well.
Patch by Evgeniy Stepanov!
llvm-svn: 145781
2011-12-03 23:49:37 +00:00
Chad Rosier
d1968c9ed6
[arm-fast-isel] Unaligned stores of floats require special care.
...
rdar://10510150
llvm-svn: 145742
2011-12-03 02:21:57 +00:00
Chad Rosier
b3b2871bbf
[arm-fast-isel] After promoting a function parameter be sure to update the
...
argument value type. Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467
llvm-svn: 145701
2011-12-02 20:25:18 +00:00
Eli Friedman
2d9e4aa665
Make GlobalMerge honor the preferred alignment on globals without an explicitly specified alignment.
...
<rdar://problem/10497732>.
llvm-svn: 145523
2011-11-30 21:54:15 +00:00
Jakob Stoklund Olesen
f227c539d4
FileCheckize.
...
llvm-svn: 145452
2011-11-29 23:09:16 +00:00
Chad Rosier
0ff2f46d12
If fast-isel fails, remove dead instructions generated during the failed
...
attempt.
llvm-svn: 145425
2011-11-29 19:40:47 +00:00
Evan Cheng
567aa3dfb3
DAG combine should not increase alignment of loads / stores with alignment less
...
than ABI alignment. These are loads / stores from / to "packed" data structures.
Their alignments are intentionally under-specified.
rdar://10301431
llvm-svn: 145273
2011-11-28 20:42:56 +00:00
Chris Lattner
9d1e8420ff
Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic.
...
llvm-svn: 145171
2011-11-27 06:54:59 +00:00
Chad Rosier
2673f8862f
When fast iseling a GEP, accumulate the offset rather than emitting a series of
...
ADDs. MaxOffs is used as a threshold to limit the size of the offset. Tradeoffs
being: (1) If we can't materialize the large constant then we'll cause fast-isel
to bail. (2) Too large of an offset can't be directly encoded in the ADD
resulting in a MOV+ADD. Generally not a bad thing because otherwise we would
have had ADD+ADD, but on Thumb this turns into a MOVS+MOVT+ADD. Working on a fix
for that. (3) Conversely, too low of a threshold we'll miss opportunities to
coalesce ADDs.
rdar://10412592
llvm-svn: 144886
2011-11-17 07:15:58 +00:00
Evan Cheng
47d8f8af84
Add vmov.f32 to materialize f32 immediate splats which cannot be handled by
...
integer variants. rdar://10437054
llvm-svn: 144608
2011-11-15 02:12:34 +00:00
Jim Grosbach
4a2f107b04
ARM VLDR/VSTR instructions don't need a size suffix.
...
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
llvm-svn: 144583
2011-11-14 23:03:21 +00:00
Chad Rosier
b107c825eb
Add newline to end of file. Thanks, Eli.
...
llvm-svn: 144579
2011-11-14 22:48:33 +00:00
Chad Rosier
48b92815e0
Add support for inlining small memcpys.
...
rdar://10412592
llvm-svn: 144578
2011-11-14 22:46:17 +00:00
Chad Rosier
8aa8f14940
Fix a performance regression from r144565. Positive offsets were being lowered
...
into registers, rather then encoded directly in the load/store.
llvm-svn: 144576
2011-11-14 22:34:48 +00:00
Chad Rosier
65395ac4d0
Add support for Thumb load/stores with negative offsets.
...
rdar://10412592
llvm-svn: 144565
2011-11-14 20:22:27 +00:00
Jakob Stoklund Olesen
6035535c96
Fix early-clobber handling in shrinkToUses.
...
I broke this in r144515, it affected most ARM testers.
<rdar://problem/10441389>
llvm-svn: 144547
2011-11-14 18:45:38 +00:00
Jakob Stoklund Olesen
83d6dda738
Delete stale comment.
...
llvm-svn: 144542
2011-11-14 18:03:05 +00:00
Chad Rosier
0e5094ca87
Add support for ARM halfword load/stores and signed byte loads with negative
...
offsets.
rdar://10412592
llvm-svn: 144518
2011-11-14 04:09:28 +00:00
Chad Rosier
58ab241006
The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall.
...
llvm-svn: 144494
2011-11-13 09:44:21 +00:00
Chad Rosier
8cfccc356e
Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures.
...
llvm-svn: 144492
2011-11-13 05:14:43 +00:00
Chad Rosier
acd199b5a4
Add support for emitting both signed- and zero-extend loads. Fix
...
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3). This enables a load followed by an integer
extend to be folded into a single load.
For example:
ldrb r1, [r0] ldrb r1, [r0]
uxtb r2, r1 =>
mov r3, r2 mov r3, r1
llvm-svn: 144488
2011-11-13 02:23:59 +00:00
Jakob Stoklund Olesen
d0ddec5771
Delete the 'standard' spiller with used the old spilling framework.
...
The current register allocators all use the inline spiller.
llvm-svn: 144477
2011-11-12 23:29:02 +00:00
Jakob Stoklund Olesen
9195bec6e7
RAGreedy is better about hinting now.
...
Or maybe we are just getting lucky.
llvm-svn: 144473
2011-11-12 22:39:37 +00:00
Jakob Stoklund Olesen
4aa9c6888f
Linear scan is going away.
...
llvm-svn: 144472
2011-11-12 22:39:34 +00:00
Jakob Stoklund Olesen
e1b1bbb882
XFAIL test that depends on linear scan to remove dead code.
...
Filed PR11364 to track the problem. Should the register allocator
eliminate dead code?
llvm-svn: 144471
2011-11-12 22:39:30 +00:00
Jakob Stoklund Olesen
94ce588b20
Switch a few tests off linearscan.
...
llvm-svn: 144460
2011-11-12 19:53:52 +00:00
Eli Friedman
8563e57e38
Don't try to form pre/post-indexed loads/stores until after LegalizeDAG runs. Fixes PR11029.
...
llvm-svn: 144438
2011-11-12 00:35:34 +00:00
Chad Rosier
a2a0fbeded
Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.
...
llvm-svn: 144426
2011-11-11 23:31:03 +00:00
Chad Rosier
88ab27405f
Loosen test by using REs. Approved by Devang.
...
llvm-svn: 144425
2011-11-11 23:25:38 +00:00
Andrew Trick
6ff75a5d8d
Preserve MachineMemOperands in ARMLoadStoreOptimizer.
...
Fixes PR8113.
llvm-svn: 144409
2011-11-11 22:18:09 +00:00
Chad Rosier
feb72bfc08
Add support for using immediates with select instructions.
...
rdar://10412592
llvm-svn: 144376
2011-11-11 06:20:39 +00:00
Eli Friedman
285b451941
Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.
...
llvm-svn: 144361
2011-11-11 03:16:38 +00:00
Chad Rosier
ac92994773
Add support for using MVN to materialize negative constants.
...
rdar://10412592
llvm-svn: 144348
2011-11-11 00:36:21 +00:00
Chad Rosier
7b7dced006
When in ARM mode, LDRH/STRH require special handling of negative offsets.
...
For correctness, disable this for now.
rdar://10418009
llvm-svn: 144316
2011-11-10 21:09:49 +00:00
Chad Rosier
69cdae5eb9
For immediate encodings of icmp, zero or sign extend first. Then
...
determine if the value is negative and flip the sign accordingly.
rdar://10422026
llvm-svn: 144258
2011-11-10 01:30:39 +00:00
Eli Friedman
c93f8aa514
Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.
...
llvm-svn: 144241
2011-11-09 23:36:02 +00:00
Eli Friedman
b01f15653c
Add check so we don't try to perform an impossible transformation. Fixes issue from PR11319.
...
llvm-svn: 144216
2011-11-09 22:25:12 +00:00
Chad Rosier
228dc76221
Use REs to remove dependencies on the register allocation order.
...
llvm-svn: 144209
2011-11-09 20:06:13 +00:00
Chad Rosier
e32fed6868
Add support for encoding immediates in icmp and fcmp. Hopefully, this will
...
remove a fair number of unnecessary materialized constants.
rdar://10412592
llvm-svn: 144163
2011-11-09 03:22:02 +00:00
Evan Cheng
08e61752f2
Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs.
...
llvm-svn: 144123
2011-11-08 21:21:09 +00:00