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Commit Graph

141 Commits

Author SHA1 Message Date
Dale Johannesen
cda84103ff get rid of some non-DebugLoc getTargetNode variants.
llvm-svn: 63909
2009-02-06 02:08:06 +00:00
Dale Johannesen
e95c76b65e Get rid of one more non-DebugLoc getNode and
its corresponding getTargetNode.  Lots of
caller changes.

llvm-svn: 63904
2009-02-06 01:31:28 +00:00
Dan Gohman
6fcee67989 Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.

To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.

llvm-svn: 62275
2009-01-15 19:20:50 +00:00
Evan Cheng
fc73640f83 Preliminary ARM debug support based on patch by Mikael of FlexyCore.
llvm-svn: 60851
2008-12-10 21:54:21 +00:00
Dan Gohman
6be47e9542 Update a comment.
llvm-svn: 60484
2008-12-03 17:10:41 +00:00
Dan Gohman
cd4b68bee9 Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.

The impact on most targets is that AddToISelQueue calls can be simply removed.

In the x86 target, there are two additional notable changes.

The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.

Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.

llvm-svn: 58748
2008-11-05 04:14:16 +00:00
David Greene
93f9f0f718 Have TableGen emit setSubgraphColor calls under control of a -gen-debug
flag.  Then in a debugger developers can set breakpoints at these calls
to see waht is about to be selected and what the resulting subgraph
looks like.  This really helps when debugging instruction selection.

llvm-svn: 58278
2008-10-27 21:56:29 +00:00
Dan Gohman
00034b1416 Avoid creating two TargetLowering objects for each target.
Instead, just create one, and make sure everything that needs
it can access it. Previously most of the SelectionDAGISel
subclasses all had their own TargetLowering object, which was
redundant with the TargetLowering object in the TargetMachine
subclasses, except on Sparc, where SparcTargetMachine
didn't have a TargetLowering object. Change Sparc to work
more like the other targets here.

llvm-svn: 57016
2008-10-03 16:55:19 +00:00
Evan Cheng
b44e839f76 Cosmetic.
llvm-svn: 56299
2008-09-18 07:24:33 +00:00
Dan Gohman
89660301e3 Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159
2008-09-12 16:56:44 +00:00
Gabor Greif
86c795a8ca erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
llvm-svn: 55504
2008-08-28 21:40:38 +00:00
Gabor Greif
4b86114f92 disallow direct access to SDValue::ResNo, provide a getter instead
llvm-svn: 55394
2008-08-26 22:36:50 +00:00
Dan Gohman
a9d5f9b006 Move the point at which FastISel taps into the SelectionDAGISel
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.

Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.

To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.

llvm-svn: 55219
2008-08-23 02:25:05 +00:00
Dan Gohman
4b801d38a1 Simplify SelectRoot's interface, and factor out some common code
from all targets.

llvm-svn: 55124
2008-08-21 16:36:34 +00:00
Dan Gohman
9742f7772d Rename SDOperand to SDValue.
llvm-svn: 54128
2008-07-27 21:46:04 +00:00
Dan Gohman
8981962672 Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.

Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.

This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.

These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.

llvm-svn: 53728
2008-07-17 19:10:17 +00:00
Dan Gohman
955fdc7a4c Add explicit keywords.
llvm-svn: 53179
2008-07-07 18:00:37 +00:00
Evan Cheng
3f664b6fd3 Split scheduling from instruction selection.
llvm-svn: 52923
2008-06-30 20:45:06 +00:00
Duncan Sands
d634afe3aa Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).

llvm-svn: 52044
2008-06-06 12:08:01 +00:00
Evan Cheng
1c67dcaae7 Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.
llvm-svn: 46724
2008-02-04 23:06:48 +00:00
Chris Lattner
e926ece00b explicitly include Compiler.h instead of getting it from tblgen in the middle of a class.
llvm-svn: 46676
2008-02-03 05:43:57 +00:00
Chris Lattner
df36b95e00 don't do ReplaceUses on a result that doesn't exist.
llvm-svn: 46673
2008-02-03 03:20:59 +00:00
Evan Cheng
c57ec111f2 SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.

llvm-svn: 46659
2008-02-02 04:07:54 +00:00
Dan Gohman
13d1327796 Factor the addressing mode and the load/store VT out of LoadSDNode
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.

llvm-svn: 46538
2008-01-30 00:15:11 +00:00
Chris Lattner
96167aa93c Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled.  Given this expanded name, we can start 
moving other stuff into it.  For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.

llvm-svn: 45467
2007-12-31 04:13:23 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Dan Gohman
6df332f0cb Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.

llvm-svn: 42762
2007-10-08 18:33:35 +00:00
Evan Cheng
abcf3842bb Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
llvm-svn: 38501
2007-07-10 18:08:01 +00:00
Evan Cheng
2403cc41ea Unfortunately we now require C++ code to isel Bcc, conditional moves, etc.
llvm-svn: 37896
2007-07-05 07:15:27 +00:00
Evan Cheng
9f0ffdf4b3 Add PredicateOperand to all ARM instructions that have the condition field.
llvm-svn: 37066
2007-05-15 01:29:07 +00:00
Chris Lattner
844e3a4191 match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll
llvm-svn: 36660
2007-05-03 00:32:00 +00:00
Evan Cheng
8d374caead Fix naming inconsistencies.
llvm-svn: 35163
2007-03-19 07:48:02 +00:00
Evan Cheng
7cbf4c4582 Special LDR instructions to load from non-pc-relative constantpools. These are
rematerializable. Only used for constant generation for now.

llvm-svn: 35162
2007-03-19 07:20:03 +00:00
Evan Cheng
7cbde8351a AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2]
llvm-svn: 35088
2007-03-13 21:05:54 +00:00
Evan Cheng
fe7242e9bb Get rid of references to iostream.
llvm-svn: 34009
2007-02-07 21:18:32 +00:00
Evan Cheng
b3ff5f65d4 Select add FI, c correctly.
llvm-svn: 33960
2007-02-06 09:11:20 +00:00
Evan Cheng
c4ba711e91 - Store val, [sp, c] must be selected to tSTRsp.
- If c does not fit in the offset field, materialize sp + c into a register
  using tADDhirr.

llvm-svn: 33944
2007-02-06 00:22:06 +00:00
Evan Cheng
99a2f7d598 Change the operand orders to t_addrmode_s* to make it easier to morph
instructions that use these address modes to instructions that use
t_addrmode_sp.

llvm-svn: 33651
2007-01-30 02:35:32 +00:00
Evan Cheng
c6db78ab84 Use PC relative ldr to load from a constantpool in Thumb mode.
llvm-svn: 33484
2007-01-24 08:53:17 +00:00
Evan Cheng
1630c86beb Allow [ fi#c, imm ] as ARM load / store addresses.
llvm-svn: 33474
2007-01-24 02:45:25 +00:00
Evan Cheng
fa613cdd06 Various Thumb mode load / store isel bug fixes.
llvm-svn: 33472
2007-01-24 02:21:22 +00:00
Evan Cheng
5f947e4e2f - Reorg Thumb load / store instructions. Combine each rr and ri pair of
instructions into one (e.g. tLDRrr, tLDRri -> tLDR).
- Thumb ldrsb and ldrsh only have the [reg, reg] address format. If the
  address is not an add, materialize a 0 immediate into a register and use
  it as the offset field.

llvm-svn: 33470
2007-01-23 22:59:13 +00:00
Evan Cheng
c6e1d453d3 ARM backend contribution from Apple.
llvm-svn: 33353
2007-01-19 07:51:42 +00:00
Lauro Ramos Venancio
97e120a71c Build constants using instructions mov/orr or mvn/eor.
llvm-svn: 33141
2007-01-12 20:35:49 +00:00
Lauro Ramos Venancio
078b85bdaa Expand SELECT (f32/f64) and FCOPYSIGN (f32/f64).
llvm-svn: 32870
2007-01-04 14:01:38 +00:00
Rafael Espindola
d1baea3471 implement missing compares
patch by Lauro
bug fixed by me

llvm-svn: 32795
2006-12-31 18:52:39 +00:00
Reid Spencer
dda168599d For PR950:
Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
   type of an function parameter was used to determine whether it should
   be sign extended or zero extended before the call. This information is
   now communicated via the function type's parameter attributes.
3. The interface to LowerCallTo had to be changed in order to accommodate
   the parameter attribute information. Although it would have been
   convenient to pass in the FunctionType itself, there isn't always one
   present in the caller. Consequently, a signedness indication for the
   result type and for each parameter was provided for in the interface
   to this method. All implementations were changed to make the adjustment
   necessary.

llvm-svn: 32788
2006-12-31 05:55:36 +00:00
Rafael Espindola
16af307d42 fix comment
llvm-svn: 32767
2006-12-29 14:28:12 +00:00
Lauro Ramos Venancio
7bfe536783 Implement SELECT_CC (f32/f64) for ARM.
llvm-svn: 32762
2006-12-28 13:11:14 +00:00
Rafael Espindola
d19ea53887 avoid using a constant table when a constant can be used inline
llvm-svn: 32580
2006-12-14 18:58:37 +00:00