Rafael Espindola
5c0443c41e
add more condition codes
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llvm-svn: 30056
2006-09-02 20:24:25 +00:00
Evan Cheng
2db7799507
Select() no longer require Result operand by reference.
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llvm-svn: 29898
2006-08-26 05:34:46 +00:00
Rafael Espindola
91954ae78f
use @ for comments
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store LR in an arbitrary stack slot
add support for writing varargs functions
llvm-svn: 29876
2006-08-25 17:55:16 +00:00
Rafael Espindola
fb63eba81c
add the "eq" condition code
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implement a movcond instruction
llvm-svn: 29857
2006-08-24 17:19:08 +00:00
Rafael Espindola
cf999a6d39
create a generic bcond instruction that has a conditional code argument
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llvm-svn: 29856
2006-08-24 16:13:15 +00:00
Rafael Espindola
9e2a2dfb2d
initial support for branches
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llvm-svn: 29854
2006-08-24 13:45:55 +00:00
Rafael Espindola
474f6c5bf1
initial support for select
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llvm-svn: 29802
2006-08-21 22:00:32 +00:00
Rafael Espindola
c255c4c434
call computeRegisterProperties
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llvm-svn: 29780
2006-08-20 01:49:49 +00:00
Rafael Espindola
ff879761c1
add a "load effective address"
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llvm-svn: 29748
2006-08-17 17:09:40 +00:00
Rafael Espindola
b98e92cb78
Declare the callee saved regs
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Remove the hard coded store and load of the link register
Implement ARMFrameInfo
llvm-svn: 29727
2006-08-16 14:43:33 +00:00
Rafael Espindola
48bed9023d
select code like
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ldr rx, [ry, #offset]
llvm-svn: 29664
2006-08-14 19:01:24 +00:00
Chris Lattner
8ca6e82bce
Eliminate use of getNode that takes a vector.
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llvm-svn: 29614
2006-08-11 17:38:39 +00:00
Chris Lattner
be2765058e
elimiante use of getNode that takes vector of operands.
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llvm-svn: 29612
2006-08-11 17:22:35 +00:00
Evan Cheng
6053206580
Match tablegen changes.
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llvm-svn: 29604
2006-08-11 09:08:15 +00:00
Rafael Espindola
f0b265b48b
fix the spill code
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llvm-svn: 29583
2006-08-09 16:41:12 +00:00
Rafael Espindola
7bfbb91f75
initial support for variable number of arguments
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llvm-svn: 29567
2006-08-08 13:02:29 +00:00
Evan Cheng
d18be1d9c1
Match tablegen isel changes.
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llvm-svn: 29549
2006-08-07 22:28:20 +00:00
Rafael Espindola
bd29d36be4
use a 'register pressure reducing' scheduler
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make sure only one move is used in a hello world
llvm-svn: 29520
2006-08-04 12:48:42 +00:00
Rafael Espindola
97918b1d11
Bug fix: always generate a RET_FLAG in LowerRET
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fixes ret_null.ll and call.ll
llvm-svn: 29519
2006-08-03 22:50:11 +00:00
Rafael Espindola
fa94338687
add and use ARMISD::RET_FLAG
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llvm-svn: 29499
2006-08-03 17:02:20 +00:00
Rafael Espindola
f11277971f
implement LowerConstantPool and LowerGlobalAddress
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llvm-svn: 29433
2006-08-01 12:58:43 +00:00
Evan Cheng
3b5f1c6248
Remove InFlightSet hack. No longer needed.
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llvm-svn: 29373
2006-07-28 00:47:19 +00:00
Rafael Espindola
2919d4ce24
implement function calling of functions with up to 4 arguments
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llvm-svn: 29274
2006-07-25 20:17:20 +00:00
Rafael Espindola
40073f5767
skeleton of a lowerCall implementation for ARM
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llvm-svn: 29159
2006-07-16 01:02:57 +00:00
Rafael Espindola
fdfaee67f5
add the memri memory operand
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this makes it possible for ldr instructions with non-zero immediate
llvm-svn: 29103
2006-07-11 11:36:48 +00:00
Rafael Espindola
071c83dff0
create the raddr addressing mode that matches any register and the frame index
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use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
llvm-svn: 29079
2006-07-10 01:41:35 +00:00
Rafael Espindola
f11f34a3d6
handle the "mov reg1, reg2" case in isMoveInstr
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llvm-svn: 28945
2006-06-27 21:52:45 +00:00
Rafael Espindola
bcba226a99
lower more then 4 formal arguments. The offset is currently hard coded.
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implement SelectFrameIndex
llvm-svn: 28751
2006-06-12 12:28:08 +00:00
Rafael Espindola
42375303a6
add R0 to liveout
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expand "ret null" (implements test/Regression/CodeGen/ARM/ret_void.ll)
note that a Flag link is missing between the copy and the branch
llvm-svn: 28691
2006-06-05 22:26:14 +00:00
Rafael Espindola
1bf57da16e
Expand ret into "CopyToReg;BRIND"
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llvm-svn: 28559
2006-05-30 17:33:19 +00:00
Evan Cheng
de0f25081a
Change RET node to include signness information of the return values. i.e.
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RET chain, value1, sign1, value2, sign2, ...
llvm-svn: 28510
2006-05-26 23:10:12 +00:00
Rafael Espindola
90eec6b0f7
port the ARM backend to use ISD::CALL instead of LowerCallTo
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llvm-svn: 28469
2006-05-25 11:00:18 +00:00
Evan Cheng
09942d3f8b
Assert if InflightSet is not cleared after instruction selecting a BB.
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llvm-svn: 28459
2006-05-25 00:24:28 +00:00
Evan Cheng
b040dd86af
Clear HandleMap and ReplaceMap after instruction selection. Or it may cause
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non-deterministic behavior.
llvm-svn: 28454
2006-05-24 20:46:25 +00:00
Chris Lattner
f604017e47
Patches to make the LLVM sources more -pedantic clean. Patch provided
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by Anton Korobeynikov! This is a step towards closing PR786.
llvm-svn: 28447
2006-05-24 17:04:05 +00:00
Rafael Espindola
bb1e2e2c52
implement minimal versions of
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ARMAsmPrinter::runOnMachineFunction
LowerFORMAL_ARGUMENTS
ARMInstrInfo::isMoveInstr
llvm-svn: 28431
2006-05-23 02:48:20 +00:00
Rafael Espindola
a0e82ff9be
implement movri
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add a stub LowerFORMAL_ARGUMENTS
llvm-svn: 28388
2006-05-18 21:45:49 +00:00
Rafael Espindola
c928207091
add an abort after every assert(0)
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llvm-svn: 28310
2006-05-15 22:34:39 +00:00
Rafael Espindola
dd49dfc0df
added a skeleton of the ARM backend
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llvm-svn: 28301
2006-05-14 22:18:28 +00:00