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55 Commits

Author SHA1 Message Date
Eli Bendersky
54b69d95ac Add a special ARM trap encoding for NaCl. 
More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html

Patch by JF Bastien

llvm-svn: 173943
 2013-01-30 16:30:19 +00:00
Silviu Baranga
dad5ffc779 Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. 
llvm-svn: 156608
 2012-05-11 09:10:54 +00:00
Owen Anderson
2d1e930b65 Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set. 
llvm-svn: 141190
 2011-10-05 17:16:40 +00:00
Jim Grosbach
43e281bec4 ARM update tests for CPS instruction. 
llvm-svn: 136472
 2011-07-29 17:39:27 +00:00
Jim Grosbach
68241cddd8 Update ARM tests for parsing and encoding of WFE, WFI and YIELD. 
llvm-svn: 136358
 2011-07-28 16:00:41 +00:00
Jim Grosbach
7b56b1cf0e ARM parsing and encoding tests for load/store exclusive instructions. 
llvm-svn: 136105
 2011-07-26 18:07:21 +00:00
Jim Grosbach
54b0cbc6ae ARM parsing and encoding tests for SBC instruction. 
llvm-svn: 135718
 2011-07-21 23:03:59 +00:00
Jim Grosbach
8d031eeb23 ARM assembly parsing support for RSC instruction. 
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.

llvm-svn: 135713
 2011-07-21 22:56:30 +00:00
Jim Grosbach
e96857fd4f ARM assembly parsing support for RSB instruction. 
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.

llvm-svn: 135712
 2011-07-21 22:37:43 +00:00
Jim Grosbach
95ce5e9b8e ARM parsing and encodings tests for saturating arithmetic insns. 
llvm-svn: 135709
 2011-07-21 22:18:28 +00:00
Jim Grosbach
9c558ee8ce Add parsing/encoding tests for ARM ORR instruction. 
llvm-svn: 135602
 2011-07-20 18:48:53 +00:00
Jim Grosbach
173559ac44 Consolidate ARM NOP encoding test. 
llvm-svn: 135600
 2011-07-20 18:39:38 +00:00
Jim Grosbach
e70c8eb49a Tweak ARM assembly parsing and printing of MSR instruction. 
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.

llvm-svn: 135532
 2011-07-19 22:45:10 +00:00
Jim Grosbach
720b8c6578 ARM assembly parsing of MRS instruction. 
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.

llvm-svn: 135527
 2011-07-19 21:59:29 +00:00
Jim Grosbach
40cce44255 Move mr[r]c[2] ARM tests and tidy up a bit. 
llvm-svn: 135517
 2011-07-19 20:28:56 +00:00
Jim Grosbach
7656c6f97e Add some testcases for ARM MLA/MLS instructions. 
llvm-svn: 135196
 2011-07-14 21:43:05 +00:00
Jim Grosbach
2ab898973a ARM MCRR/MCRR2 immediate operand range checking. 
llvm-svn: 135192
 2011-07-14 21:26:42 +00:00
Jim Grosbach
27ebbba831 ARM MCR/MCR2 assembly parsing operand constraints. 
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.

llvm-svn: 135189
 2011-07-14 21:19:17 +00:00
Jim Grosbach
09b5985799 Enable some tests we now handle correctly. 
llvm-svn: 135185
 2011-07-14 21:02:23 +00:00
Jim Grosbach
aebb9cdf68 Update ARM Assembly of LDM/STM. 
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.

llvm-svn: 135168
 2011-07-14 18:35:38 +00:00
Jim Grosbach
ebbd82a248 ARM ISB assembly parsing tests. 
llvm-svn: 135158
 2011-07-14 18:02:25 +00:00
Jim Grosbach
9bbc2007df ARM ISB instruction assembly parsing. 
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.

llvm-svn: 135156
 2011-07-14 18:00:31 +00:00
Jim Grosbach
fe9c954c0f Remove duplicate tests. 
llvm-svn: 135117
 2011-07-14 00:19:19 +00:00
Jim Grosbach
5a96cebd81 ARM Assembler support for DMB instruction. 
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".

llvm-svn: 135109
 2011-07-13 23:40:38 +00:00
Jim Grosbach
d5e74991f0 Shuffle ARM assembly tests a bit. 
llvm-svn: 135095
 2011-07-13 22:19:10 +00:00
Jim Grosbach
7c950cf36c ARM assembler support for ldmfd/stmfd mnemonics. 
llvm-svn: 133936
 2011-06-27 20:32:18 +00:00
Bruno Cardoso Lopes
0bdb365634 Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value 
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.

llvm-svn: 132324
 2011-05-31 03:33:27 +00:00
Bruno Cardoso Lopes
3a4aae57f4 Fix PR9762 
Enable the parsing of the operand "cpsr_all" for the ARM msr instruction

llvm-svn: 132026
 2011-05-25 00:35:03 +00:00
Bruno Cardoso Lopes
a5de5df6d8 Add asm parsing support w/ testcases for strex/ldrex family of instructions 
llvm-svn: 128236
 2011-03-24 21:04:58 +00:00
Owen Anderson
16fce7d4af Add support to the ARM asm parser for the register-shifted-register forms of basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA. 
llvm-svn: 127917
 2011-03-18 22:50:18 +00:00
Bruno Cardoso Lopes
ad05904e0b Add assembly parsing support for "msr" and also fix its encoding. Also add 
testcases for the disassembler to make sure it still works for "msr".

llvm-svn: 125948
 2011-02-18 19:45:59 +00:00
Bruno Cardoso Lopes
e65a98b127 Fix encoding and add parsing support for the arm/thumb CPS instruction: 
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
  from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
  wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.

llvm-svn: 125489
 2011-02-14 13:09:44 +00:00
Bruno Cardoso Lopes
0ce5b0f4a8 Add support for parsing dmb/dsb instructions 
llvm-svn: 125055
 2011-02-07 22:09:15 +00:00
Bruno Cardoso Lopes
2d6bd03b18 fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions 
llvm-svn: 124288
 2011-01-26 13:28:14 +00:00
Bruno Cardoso Lopes
2f96371a7a Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm", 
qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.

llvm-svn: 123975
 2011-01-21 14:07:40 +00:00
Bruno Cardoso Lopes
dc3853d7b5 Add testcases for clz encoding 
llvm-svn: 123937
 2011-01-20 19:27:16 +00:00
Bruno Cardoso Lopes
6aeb2e320f Fix the encoding and parsing of clrex instruction 
llvm-svn: 123936
 2011-01-20 19:18:32 +00:00
Bruno Cardoso Lopes
3584c02d83 - Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present 
in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.

llvm-svn: 123927
 2011-01-20 18:06:58 +00:00
Bruno Cardoso Lopes
0f7a30b1cb Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc 
llvm-svn: 123837
 2011-01-19 16:56:52 +00:00
Bruno Cardoso Lopes
82c6fe3dfe Fix MRS encoding for arm and thumb. 
llvm-svn: 123778
 2011-01-18 21:31:35 +00:00
Bruno Cardoso Lopes
6e4c5af01e Fix the encoding of t2ISB by using the right class and also parse it correctly 
llvm-svn: 123776
 2011-01-18 21:17:09 +00:00
Bruno Cardoso Lopes
c1e21b06b9 Follow the current hack set and enable the correct parsing of bkpt while in thumb mode. 
llvm-svn: 123772
 2011-01-18 20:55:11 +00:00
Bruno Cardoso Lopes
94247155c4 Add support for parsing and encoding ARM's official syntax for the BFI instruction 
llvm-svn: 123770
 2011-01-18 20:45:56 +00:00
Daniel Dunbar
fbc0b96c34 McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out the 
carry setting flag from the mnemonic.

Note that this currently involves me disabling a number of working cases in
arm_instructions.s, this is a hopefully short term evil which will be rapidly
fixed (and greatly surpassed), assuming my current approach flies.

llvm-svn: 123238
 2011-01-11 15:59:50 +00:00
Kevin Enderby
6b3ae489f8 Add some more MC tests for ARM arithmetic instructions that update or don't 
update the condition codes.  These come from my test generator and are just
the ones that MC currently assembles correctly.

llvm-svn: 121830
 2010-12-15 01:24:36 +00:00
Kevin Enderby
55cb19813e Add support for parsing ARM arithmetic instructions that update or don't update 
the condition codes.  Where the ones that do have an 's' suffix and the ones
that don't don't have the suffix.  The trick is if MatchInstructionImpl() fails
we try again after adding a CCOut operand with the correct value and removing
the 's' if present.  Four simple test cases added for now, lots more to come.

llvm-svn: 121401
 2010-12-09 19:19:43 +00:00
Bill Wendling
a472e7be70 Add encoding for ARM "trap" instruction. 
llvm-svn: 119938
 2010-11-21 11:05:29 +00:00
Bill Wendling
ef43273c51 Add support for parsing the writeback ("!") token. 
llvm-svn: 119761
 2010-11-18 23:43:05 +00:00
Bill Wendling
e15bf6b98d Test encodings for LDM and STM. 
llvm-svn: 119315
 2010-11-16 01:38:20 +00:00
Bill Wendling
1546322a9c Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work 
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.

llvm-svn: 118094
 2010-11-02 22:31:46 +00:00