Vincent Lejeune
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4a8c23c168
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R600: Non vector only instruction can be scheduled on trans unit
llvm-svn: 189980
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2013-09-04 19:53:46 +00:00 |
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Tom Stellard
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c6c9cd5b09
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Revert "R600: Non vector only instruction can be scheduled on trans unit"
This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6.
llvm-svn: 187526
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2013-07-31 20:43:27 +00:00 |
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Vincent Lejeune
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2100f94811
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R600: Non vector only instruction can be scheduled on trans unit
llvm-svn: 187514
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2013-07-31 19:31:56 +00:00 |
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Tom Stellard
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e60bb5f272
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R600: Use KCache for kernel arguments
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186918
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2013-07-23 01:48:18 +00:00 |
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Tom Stellard
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0faf53682e
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R600/SI: Add a calling convention for compute shaders
llvm-svn: 183137
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2013-06-03 17:40:11 +00:00 |
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Vincent Lejeune
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55871f8f8a
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R600: use capital letter for PV channel
llvm-svn: 183107
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2013-06-03 15:44:35 +00:00 |
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Tom Stellard
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6cdacd1792
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R600: Fix rotr.ll on non-asserts builds
The -debug-only option is only available on asserts builds.
llvm-svn: 182291
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2013-05-20 15:28:48 +00:00 |
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Tom Stellard
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d72698331e
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R600/SI: Add pattern for rotr
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182286
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2013-05-20 15:02:24 +00:00 |
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Tom Stellard
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5ca265d214
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R600: Swap the legality of rotl and rotr
The hardware supports rotr and not rotl.
llvm-svn: 182285
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2013-05-20 15:02:19 +00:00 |
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