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Commit Graph

152097 Commits

Author SHA1 Message Date
Vitaly Buka
7e3789c116 [asan] Copy arguments passed by value into explicit allocas for ASan
Summary:
  ASan determines the stack layout from alloca instructions. Since
arguments marked as "byval" do not have an explicit alloca instruction, ASan
does not produce red zones for them. This commit produces an explicit alloca
instruction and copies the byval argument into the allocated memory so that red
zones are produced.

  Submitted on behalf of @morehouse (Matt Morehouse)

  Reviewers: eugenis, vitalybuka

  Reviewed By: eugenis

  Subscribers: hiraditya, llvm-commits

  Differential Revision: https://reviews.llvm.org/D34789

llvm-svn: 308387
2017-07-18 22:28:03 +00:00
Saleem Abdulrasool
a300298c79 Object: rename parameter from DLLName to ImportName
When I originally wrote this code, I neglected the fact that the import
library may be created for executables.  This name is not the name of
the DLL, but rather the name for the imported module.  It will be
embedded into the IAT/ILT reference.  Rename it to make it more obvious.
NFC.

llvm-svn: 308384
2017-07-18 22:11:01 +00:00
Saleem Abdulrasool
3ba7c8d78b Object: handle extensions properly in def files
When given an extension as part of the `library` directive in a def
file, the extension is preserved/honoured by link/lib.  Behave similarly
when parsing the def file.  This requires checking if a native extension
is provided as a keyword parameter.  If no extension is present, append
a standard `.dll` or `.exe` extension.

This is best tested via lld, and I will add tests there as a follow up.

llvm-svn: 308383
2017-07-18 22:11:00 +00:00
Martell Malone
4ec77fc2c7 llvm: add llvm-dlltool support to the archiver
A PE COFF spec compliant import library generator.
Intended to be used with mingw-w64.

Supports:
PE COFF spec (section 8, Import Library Format)
PE COFF spec (Aux Format 3: Weak Externals)

Reviewed By: ruiu
Differential Revision: https://reviews.llvm.org/D29892

This reapplies rL308329, which was reverted in rL308374

llvm-svn: 308379
2017-07-18 21:26:38 +00:00
Lang Hames
3b9218a913 [RuntimeDyld][MachO/ARM] Don't add a redundant relocation entry.
We only need to add this entry once for it to be fixed up.

llvm-svn: 308375
2017-07-18 21:12:03 +00:00
Rui Ueyama
b21f190999 Revert r308329: llvm: add llvm-dlltool support to the archiver
This reverts commit r308329 because it broke buildbots.

llvm-svn: 308374
2017-07-18 21:07:13 +00:00
Martell Malone
690c7a43f6 llvm: fix -Wcast gcc warn error from rL308329
llvm-svn: 308360
2017-07-18 20:58:21 +00:00
Petr Hosek
59aa9a9aad [CMake] Set toolchain tools in cross-target runtimes build
This is needed for runtimes build to work on Darwin.

Differential Revision: https://reviews.llvm.org/D35343

llvm-svn: 308359
2017-07-18 20:54:02 +00:00
Mandeep Singh Grang
a0b275cd4a [COFF, ARM64] Reserve X18 register by default
Reviewers: compnerd, rnk, ruiu, mstorsjo

Reviewed By: mstorsjo

Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D35531

llvm-svn: 308358
2017-07-18 20:41:33 +00:00
Jakub Kuderski
8ea3fd17cd [Dominators] Improve error checking in deleteEdge
Summary: This patch improves error detection in deleteEdge. It asserts that the edge doesn't exist in the CFG and that DomTree knew about this edge before.

Reviewers: dberlin, grosser, brzycki, sanjoy

Reviewed By: dberlin

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35571

llvm-svn: 308354
2017-07-18 20:19:52 +00:00
Nirav Dave
2e307633f3 [DAG] Improve Aliasing of operations to static alloca
Re-recommiting after landing DAG extension-crash fix.

Recommiting after adding check to avoid miscomputing alias information
on addresses of the same base but different subindices.

Memory accesses offset from frame indices may alias, e.g., we
may merge write from function arguments passed on the stack when they
are contiguous. As a result, when checking aliasing, we consider the
underlying frame index's offset from the stack pointer.

Static allocs are realized as stack objects in SelectionDAG, but its
offset is not set until post-DAG causing DAGCombiner's alias check to
consider access to static allocas to frequently alias. Modify isAlias
to consider access between static allocas and access from other frame
objects to be considered aliasing.

Many test changes are included here. Most are fixes for tests which
indirectly relied on our aliasing ability and needed to be modified to
preserve their original intent.

The remaining tests have minor improvements due to relaxed
ordering. The exception is CodeGen/X86/2011-10-19-widen_vselect.ll
which has a minor degradation dispite though the pre-legalized DAG is
improved.

Reviewers: rnk, mkuper, jonpa, hfinkel, uweigand

Reviewed By: rnk

Subscribers: sdardis, nemanjai, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D33345

llvm-svn: 308350
2017-07-18 20:06:24 +00:00
Nirav Dave
fc4e5d56b2 [DAG] Reverse node replacement in extension operation. NFCI.
Reorder replacements to be user first in preparation for multi-level
folding to premptively avoid inadvertantly deleting later nodes from
sharing found from replacement.

llvm-svn: 308348
2017-07-18 19:49:20 +00:00
Brian Gesiak
202417f2b1 [opt-viewer] Handle file names that contain '#'
Summary:
When using opt-viewer.py with files with '#' in their name, such as
'foo#bar.cpp', opt-viewer.py would generate links such as
'/path/to/foo#bar.cpp.opt.yaml#L42'. In this case, the link is
interpreted by browsers as a link to the file '/path/to/foo', and to the
section within that file with ID 'bar.cpp.opt.yaml#L42'.

To work around this issue, replace '#' with '_' in file names and links
in opt-viewer.py.

Reviewers: anemet, davidxl

Reviewed By: davidxl

Subscribers: llvm-commits, fhahn

Differential Revision: https://reviews.llvm.org/D34646

llvm-svn: 308346
2017-07-18 19:25:34 +00:00
James Y Knight
d303a3f101 [Sparc] Added software multiplication/division feature
Added a feature to the Sparc back-end that replaces the integer multiply and
divide instructions with calls to .mul/.sdiv/.udiv. This is a step towards
having full v7 support.

Patch by: Eric Kedaigle
Differential Revision: https://reviews.llvm.org/D35500

llvm-svn: 308343
2017-07-18 19:08:38 +00:00
Kostya Serebryany
942eea9a0e [libFuzzer] when adding a reduced input print REDUCED instead of NEW
llvm-svn: 308336
2017-07-18 18:47:36 +00:00
Hiroshi Inoue
7c30291c1b fix typos in a document; NFC
llvm-svn: 308331
2017-07-18 17:52:47 +00:00
Nirav Dave
888f48a63e [DAG] Avoid deleting nodes before combining them.
When replacing a node and it's operand, replacing the operand node may
cause the deletion of the original node leading to an assertion
failure. Case around these replacements to avoid this without relying
on inspecting the DELETED_NODE opcode in various extend
dagcombiner cases.

Fixes PR32515.

Reviewers: dbabokin, RKSimon, davide, chandlerc

Subscribers: chandlerc, llvm-commits

Differential Revision: https://reviews.llvm.org/D34095

llvm-svn: 308330
2017-07-18 17:39:15 +00:00
Martell Malone
644494b9e0 llvm: add llvm-dlltool support to the archiver
A PE COFF spec compliant import library generator.
Intended to be used with mingw-w64.

Supports:
PE COFF spec (section 8, Import Library Format)
PE COFF spec (Aux Format 3: Weak Externals)

Reviewed By: ruiu

Differential Revision: https://reviews.llvm.org/D29892

llvm-svn: 308329
2017-07-18 17:39:11 +00:00
Matt Arsenault
f6d3214a17 AMDGPU: Annotate necessity of flat-scratch-init
As an approximation of the existing handling to avoid
regressions. Fixes using too many registers with calls
on subtargets with the SGPR allocation bug.

llvm-svn: 308326
2017-07-18 16:44:58 +00:00
Matt Arsenault
b8eb99e870 AMDGPU: Figure out private memory regs after lowering
Introduce pseudo-registers for registers needed for stack
access, which are replaced during finalizeLowering.
Note these pseudo-registers are currently only used for the
used register location, and not for determining their
input argument register.

This is better because it avoids the need to try to predict
whether a call will be emitted from the IR, and also
detects stack objects introduced by legalization.

Test changes are from the HasStackObjects check being more
accurate since stack objects introduced during legalization
are now known.

llvm-svn: 308325
2017-07-18 16:44:56 +00:00
Geoff Berry
1cfe6f1f1d [AArch64][Falkor] Avoid HW prefetcher tag collisions (step 2)
Summary:
Avoid HW prefetcher instruction tag collisions in loops by inserting
MOVs to change the base address register of strided loads.

Reviewers: t.p.northover, mcrosier

Subscribers: aemerson, rengolin, javed.absar, kristof.beyls, hfinkel, llvm-commits

Differential Revision: https://reviews.llvm.org/D35366

llvm-svn: 308324
2017-07-18 16:14:22 +00:00
Simon Pilgrim
eeed91cfa1 [X86][AVX] Regenerate shift test to show constant broadcast comment
llvm-svn: 308323
2017-07-18 16:07:12 +00:00
Simon Pilgrim
8a515df296 [x86, CGP] increase memcmp() expansion up to 4 load pairs
It should be a win to avoid going out to the system lib for all small memcmp() calls using scalar ops. For x86 32-bit, this means most everything up to 16 bytes. For 64-bit, that doubles because we can do 8-byte loads.

Notes:

    Reduced from 4 to 2 loads for -Os behavior, which might not be optimal in all cases. It's effectively a question of how much do we trust the system implementation. Linux and macOS (and Windows I assume, but did not test) have optimized memcmp() code for x86, so it's probably not bad either way? PPC is using 8/4 for defaults on these. We do not expand at all for -Oz.

    There are still potential improvements to make for the CGP expansion IR and/or lowering such as avoiding select-of-constants (D34904) and not doing zexts to the max load type before doing a compare.

    We have special-case SSE/AVX codegen for (memcmp(x, y, 16/32) == 0) that will no longer be produced after this patch. I've shown the experimental justification for that change in PR33329:

https://bugs.llvm.org/show_bug.cgi?id=33329#c12
TLDR: While the vector code is a likely winner, we can't guarantee that it's a winner in all cases on all CPUs, so I'm willing to sacrifice it for the greater good of expanding all small memcmp(). If we want to resurrect that codegen, it can be done by adjusting the CGP params or poking a hole to let those fall-through the CGP expansion.

Committed on behalf of Sanjay Patel

Differential Revision: https://reviews.llvm.org/D35067

llvm-svn: 308322
2017-07-18 15:55:30 +00:00
Frederich Munch
ecf072ed61 Make EHFrames available to sub-classes of RTDyldMemoryManager.
Summary: This information can be useful; and in the case of Win64, necessary for getting exceptions to work in the JIT.

Reviewers: lhames

Reviewed By: lhames

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35102

llvm-svn: 308321
2017-07-18 15:50:28 +00:00
Davide Italiano
9e4866a81c [TRE] Simplify canTRE() a bit using all_of(). NFCI.
This has a ~11 years old FIXME, which may not be true today.
We might consider removing this code altogether.

llvm-svn: 308319
2017-07-18 15:42:59 +00:00
Sumanth Gundapaneni
8f562430f0 [Hexagon] Emit lookup tables in text section based on a flag
The flag "-hexagon-emit-lut-text" (defaulted to false) is added to decide
on where to keep the switch generated lookup table.
Differential Revision: https://reviews.llvm.org/D34818

llvm-svn: 308316
2017-07-18 15:31:37 +00:00
Nicolai Haehnle
622fc6ece0 AMDGPU: Fix crash when folding immediates into multiple uses
Summary:
When an immediate is folded by constant folding, we re-scan the entire
use list for two reasons:

1. The constant folding may have created a new use of the same reg.
2. The constant folding may have removed an additional use in the list
   we're currently traversing (e.g., constant folding an S_ADD_I32 c, c).

However, this could previously lead to a crash when an unrelated use was
added twice into the FoldList. Since we re-scan the whole list anyway, we
might as well just clear the FoldList again before we do so.

Using a MIR test to show this because real code seems to trigger the issue
only in connection with some really subtle control flow structures.

Fixes GL45-CTS.shading_language_420pack.binding_images on gfx9.

Reviewers: arsenm

Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D35416

llvm-svn: 308314
2017-07-18 14:54:41 +00:00
Nirav Dave
0f1a225e39 [DAG] Allow base element type of store merge type to also be a vector.
Correctly calculate merged vector size if MemVT is already a vector.

llvm-svn: 308312
2017-07-18 14:39:09 +00:00
Simon Pilgrim
fdf503383f [X86] Add optsize and minsize memcmp tests (D35067)
llvm-svn: 308311
2017-07-18 14:26:07 +00:00
Sam Kolton
0793049df3 [AMDGPU] resubmit r308179: CodeGen: check dst operand type to determine if omod is supported for VOP3 instructions
llvm-svn: 308310
2017-07-18 14:23:26 +00:00
Simon Pilgrim
acb717e2d5 [X86] Added cmov target to memcmp test
As discussed by @spatel on D35067:

"I added the cmov attribute to the 32-bit codegen test because it removes some noise for that file. I think the intent for the SSE vs no-SSE runs is to show the potential difference for the 16 and 32 byte cases rather than the lack of cmov (which has been available for all CPUs since SSE1, so that's why it shows up automatically with -mattr=sse2)."

llvm-svn: 308309
2017-07-18 14:19:34 +00:00
Daniel Sanders
5bdf5fa992 [globalisel][tablegen] Enable the import of rules involving fma.
Summary:
G_FMA was recently added to GlobalISel which enables the import of rules
involving fma. Add the mapping to allow it.

Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar

Reviewed By: rovka

Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits

Differential Revision: https://reviews.llvm.org/D35130

llvm-svn: 308308
2017-07-18 14:10:07 +00:00
Hiroshi Inoue
309f36a350 fix formatting issue; NFC
llvm-svn: 308305
2017-07-18 13:31:40 +00:00
Dmitry Preobrazhensky
20c04a1a9c [AMDGPU][MC] Corrected disassembler for proper decoding of v_mqsad_u32_u8
See Bug 33639: https://bugs.llvm.org//show_bug.cgi?id=33639

Reviewers: vpykhtin, artem.tamazov

Differential Revision: https://reviews.llvm.org/D34892

llvm-svn: 308303
2017-07-18 13:12:48 +00:00
Simon Pilgrim
aada93f97c [DAGCombine] Fix issue with out of bound constant rotation (PR33828)
Take the modulo of rotations by a constant greater than or equal to the bit-width

llvm-svn: 308302
2017-07-18 12:31:46 +00:00
Stefan Maksimovic
d4e97a7afd [mips] Alter register classes for MSA pseudo f16 instructions
This change introduces additional machine instructions in functions
dealing with the expansion of msa pseudo f16 instructions due to
register classes being inappropriate when checked with machine
verifier.

Differential Revision: https://reviews.llvm.org/D34276

llvm-svn: 308301
2017-07-18 12:05:35 +00:00
Dorit Nuzman
275f2254fd PSCEV] Create AddRec for Phis in cases of possible integer overflow,
using runtime checks

Extend the SCEVPredicateRewriter to work a bit harder when it encounters an
UnknownSCEV for a Phi node; Try to build an AddRecurrence also for Phi nodes
whose update chain involves casts that can be ignored under the proper runtime
overflow test. This is one step towards addressing PR30654.

Differential revision: http://reviews.llvm.org/D30041

llvm-svn: 308299
2017-07-18 11:57:08 +00:00
Alexander Potapenko
18abc9245f [sancov] Fix PR33732
Coverage hooks that take less-than-64-bit-integers as parameters need the
zeroext parameter attribute (http://llvm.org/docs/LangRef.html#paramattrs)
to make sure they are properly extended by the x86_64 ABI.

llvm-svn: 308296
2017-07-18 11:47:56 +00:00
Simon Pilgrim
6b5ea50a12 [X86][AVX512] Add ISD::ROTL/ISD::ROTR constant folding tests
llvm-svn: 308295
2017-07-18 11:18:38 +00:00
Dmitry Preobrazhensky
439041b87f [AMDGPU][MC] Optimized IsRegIntersect function
Optimized IsRegIntersect by using MCRegAliasIterator

See Bug 33800: https://bugs.llvm.org//show_bug.cgi?id=33800

Reviewers: arsenm, artem.tamazov

Differential Revision: https://reviews.llvm.org/D35452

llvm-svn: 308294
2017-07-18 11:14:02 +00:00
George Rimar
89cb57e606 [libOption] - Replace std::pair with helper struct. NFC.
Splitted from D35476.

llvm-svn: 308293
2017-07-18 10:59:30 +00:00
Javed Absar
374e6b7624 [ARM|CodeGen] Improve the code in FastISel
Cleaned up the code in FastISel a bit.
Had to add make_range to MCInstrDesc as that was needed and seems missing.

Reviewed by: @t.p.northover
Differential Revision: https://reviews.llvm.org/D35494

llvm-svn: 308291
2017-07-18 10:19:48 +00:00
Simon Pilgrim
141dc67bc1 [X86] Add test case for PR32282
llvm-svn: 308286
2017-07-18 10:09:40 +00:00
Diana Picus
5112f60df1 [ARM] GlobalISel: Support G_(S|U)REM for s8 and s16
Widen to s32, and then do whatever Lowering/Custom/Libcall action the
subtarget wants.

llvm-svn: 308285
2017-07-18 10:07:01 +00:00
Florian Hahn
caa2269e29 [LoopInterchange] Split up interchange.ll test case (NFC).
Summary:
Currently most tests for the loop interchange pass are in
test/Transforms/LoopInterchange/interchange.ll. This patch splits up the
large test file in smaller pieces, which makes debugging test failures
easier.

Reviewers: karthikthecool, blitz.opensource, hfinkel

Reviewed By: hfinkel

Subscribers: hfinkel, mcrosier, mkuper, mzolotukhin, mssimpso, llvm-commits

Differential Revision: https://reviews.llvm.org/D35488

llvm-svn: 308284
2017-07-18 09:47:06 +00:00
Florian Hahn
1b5c12d4ec [AArch64] Use 16 bytes as preferred function alignment on Cortex-A73.
Summary:
Using 16 byte alignment is beneficial on Cortex-A73, similar to
Cortex-A72 (added in D34961).

Reviewers: mcrosier, t.p.northover, aadg, silviu.baranga

Reviewed By: t.p.northover

Subscribers: aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D35493

llvm-svn: 308283
2017-07-18 09:31:18 +00:00
Dmitry Preobrazhensky
61261f269d [AMDGPU][MC] Added missing VOP3P opcodes
Added support of the following opcodes:
  v_pk_sub_u16
  v_pk_mad_i16
  v_pk_mad_u16

See Bug 33593: https://bugs.llvm.org//show_bug.cgi?id=33593

Reviewers: vpykhtin, artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D34890

llvm-svn: 308281
2017-07-18 09:24:10 +00:00
Jonas Paulsson
dad136fdf3 [SystemZ, AsmParser] Enable the mnemonic spell corrector.
This enables the suggestions of other mnemonics when invalid ones are
specified.

Review: Ulrich Weigand
llvm-svn: 308280
2017-07-18 09:17:00 +00:00
Diana Picus
8302a2eb1c GlobalISel: Support G_(S|U)REM widening in LegalizerHelper
Treat widening G_SREM and G_UREM the same as G_SDIV and G_UDIV. This is
going to be used in the ARM backend (and that's when the test will come
too).

llvm-svn: 308278
2017-07-18 09:08:47 +00:00
NAKAMURA Takumi
9d77e03ebd llvm/DebugInfo/CodeView/TypeStreamMerger.h: Prune a couple of \param(s), removed in r308212. [-Wdocumentation]
llvm-svn: 308276
2017-07-18 08:52:02 +00:00