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850 Commits

Author SHA1 Message Date
Duncan Sands
d1bdbd010b Eliminate the remaining uses of getTypeSize. This 
should only effect x86 when using long double.  Now
12/16 bytes are output for long double globals (the
exact amount depends on the alignment).  This brings
globals in line with the rest of LLVM: the space
reserved for an object is now always the ABI size.
One tricky point is that only 10 bytes should be
output for long double if it is a field in a packed
struct, which is the reason for the additional
argument to EmitGlobalConstant.

llvm-svn: 43688
 2007-11-05 00:04:43 +00:00
Eric Christopher
82c77dd85b clo/clz aren't supported on mips I. Keep them around for when we'll 
want them later (mips32/64).

llvm-svn: 43380
 2007-10-26 04:00:13 +00:00
Evan Cheng
0449186690 - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding. 
- Fix some copy+paste bugs.

llvm-svn: 43153
 2007-10-18 22:40:57 +00:00
Evan Cheng
c852780685 Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface. 
llvm-svn: 43150
 2007-10-18 21:29:24 +00:00
Evan Cheng
33df6a6bed Revert 42908 for now. 
llvm-svn: 42960
 2007-10-14 05:57:21 +00:00
Dan Gohman
a75e4a62e6 Change the names used for internal labels to use the current 
function symbol name instead of a codegen-assigned function
number.

Thanks Evan! :-)

llvm-svn: 42908
 2007-10-12 14:53:36 +00:00
Bruno Cardoso Lopes
257d5a5127 Position Independent Code (PIC) support [3] 
llvm-svn: 42780
 2007-10-09 03:15:11 +00:00
Bruno Cardoso Lopes
627ba10946 Position Independent Code (PIC) support [2] 
- Added a function to hold the stack location 
  where GP must be stored during LowerCALL
- AsmPrinter now emits directives based on
  relocation type
- PIC_ set to default relocation type (same as GCC)

llvm-svn: 42779
 2007-10-09 03:01:19 +00:00
Bruno Cardoso Lopes
3a48664e98 Position Independent Code (PIC) support [1] 
- Modified instruction format to handle pseudo instructions
- Added LoadAddr SDNode to load symbols.

llvm-svn: 42778
 2007-10-09 02:55:31 +00:00
Evan Cheng
f536e2f41e - Added a few target hooks to generate load / store instructions from / to any 
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.

llvm-svn: 42621
 2007-10-05 01:32:41 +00:00
Evan Cheng
5f9e291240 Allow copyRegToReg to emit cross register classes copies. 
Tested with "make check"!

llvm-svn: 42346
 2007-09-26 06:25:56 +00:00
Dan Gohman
99e8e1ff08 More explicit keywords. 
llvm-svn: 42316
 2007-09-25 20:27:06 +00:00
Bruno Cardoso Lopes
23468a24c9 Added "LoadEffective" pattern to handle stack locations. 
Fixed some comments

llvm-svn: 42271
 2007-09-24 20:15:11 +00:00
Evan Cheng
b43255bc68 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
llvm-svn: 41863
 2007-09-11 19:55:27 +00:00
Duncan Sands
c358890f73 Fold the adjust_trampoline intrinsic into 
init_trampoline.  There is now only one
trampoline intrinsic.

llvm-svn: 41841
 2007-09-11 14:10:23 +00:00
Owen Anderson
4b71e55287 Add lengthof and endof templates that hide a lot of sizeof computations. 
Patch by Sterling Stein!

llvm-svn: 41758
 2007-09-07 04:06:50 +00:00
Evan Cheng
58ea935f6f Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots. 
llvm-svn: 41597
 2007-08-30 05:52:20 +00:00
Bruno Cardoso Lopes
ff764398e6 Added method to get Mips register numbers 
Changed the stack frame layout, StackGrowsUp fits better to Mips strange stack.
Stack offset calculation bug fixed!

llvm-svn: 41529
 2007-08-28 05:13:42 +00:00
Bruno Cardoso Lopes
144486ca7e Changed stack allocation On LowerFORMAL_ARGUMENTS. 
Added comments about new stack allocation.
Expand SelectCC for i32 results

llvm-svn: 41527
 2007-08-28 05:08:16 +00:00
Bruno Cardoso Lopes
96894b2c93 Mask directive completed with CalleeSave info 
Comments for Mips directives added.

llvm-svn: 41526
 2007-08-28 05:06:17 +00:00
Bruno Cardoso Lopes
b77d5cd9d5 Added methods to record SPOffsets from LowerFORMAL_ARGUMENTS 
llvm-svn: 41525
 2007-08-28 05:04:41 +00:00
Bruno Cardoso Lopes
14e39d7bcf InlineAsm asm support for integer registers added 
llvm-svn: 41225
 2007-08-21 16:09:25 +00:00
Bruno Cardoso Lopes
4173f973e9 Instruction Itinerary attribution fixed 
llvm-svn: 41224
 2007-08-21 16:06:45 +00:00
Bruno Cardoso Lopes
40b9999770 MipsHi now has ouput flag 
MipsAdd SDNode created to add support to an Add opcode which supports input flag
Added an instruction itinerary to all instruction classes
Added branches with zero cond codes
Now call clobbers all non-callee saved registers
Call w/ register support added
Added DelaySlot to branch and load instructions
Added patterns to handle all setcc, brcond/setcc and MipsAdd instructions

llvm-svn: 41161
 2007-08-18 02:37:46 +00:00
Bruno Cardoso Lopes
3bc582fa67 Fixed stack frame addressing bug 
llvm-svn: 41160
 2007-08-18 02:19:09 +00:00
Bruno Cardoso Lopes
15cbbbb56f support for Schedule included on Mips.td 
llvm-svn: 41159
 2007-08-18 02:18:07 +00:00
Bruno Cardoso Lopes
e2909db54c Removed LowerRETURADDR, fixed small bug into LowerRET, LowerGlobalAddress 
fixed to generate instructions (add, lui) glued!

llvm-svn: 41158
 2007-08-18 02:16:30 +00:00
Bruno Cardoso Lopes
d13e0b33d1 Couple of small changes. Delay Slot handle header declared. 
Newline added after macros at function init on generated asm!

llvm-svn: 41157
 2007-08-18 02:05:24 +00:00
Bruno Cardoso Lopes
1ad2687157 Added InstrItinClass support for instruction formats 
llvm-svn: 41156
 2007-08-18 02:01:28 +00:00
Bruno Cardoso Lopes
0dce1a316c Branch Analysis and InsertNoop inserted into header files 
llvm-svn: 41155
 2007-08-18 01:59:45 +00:00
Bruno Cardoso Lopes
ae01dc5e74 createMipsDelaySlotFillerPass added to mips codegen runtime 
llvm-svn: 41154
 2007-08-18 01:58:15 +00:00
Bruno Cardoso Lopes
7bca87bebd Added Branch Analysis support 
Added InsertNoop support

llvm-svn: 41153
 2007-08-18 01:56:48 +00:00
Bruno Cardoso Lopes
c7eaab9c92 LowerRETURNADDR removed since it was wrong and does not have utility yet! 
MipsAdd opcode added

llvm-svn: 41152
 2007-08-18 01:54:09 +00:00
Bruno Cardoso Lopes
d97285f98a InstrItineraryData support on added. 
Added Mips3 ISA feature (needed when supporting R4000 machines)

llvm-svn: 41151
 2007-08-18 01:52:27 +00:00
Bruno Cardoso Lopes
bc755b9969 A Pass to insert Nops on intructions with DelaySlot 
llvm-svn: 41150
 2007-08-18 01:50:47 +00:00
Bruno Cardoso Lopes
d67580757e Mips generic fallback instruction schedule support! 
llvm-svn: 41149
 2007-08-18 01:46:44 +00:00
Dan Gohman
352de5aeb9 More explicit keywords. 
llvm-svn: 40757
 2007-08-02 21:21:54 +00:00
Duncan Sands
e8bb2c6d32 Support for trampolines, except for X86 codegen which is 
still under discussion.

llvm-svn: 40549
 2007-07-27 12:58:54 +00:00
Dan Gohman
0fc4e0cf47 Don't ignore the return value of AsmPrinter::doInitialization and 
AsmPrinter::doFinalization.

llvm-svn: 40487
 2007-07-25 19:33:14 +00:00
Evan Cheng
53cb03b583 No more noResults. 
llvm-svn: 40132
 2007-07-21 00:34:19 +00:00
Evan Cheng
8312ed6f77 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Bruno Cardoso Lopes
27f5beafb2 Added support for Mips specific GAS directives 
Fixed print immediate 
Fixed Identation on MipsISelDAGToDAG.cpp

llvm-svn: 39764
 2007-07-11 23:24:41 +00:00
Bruno Cardoso Lopes
e21704313d Added support for framepointer 
Prologue/Epilogue support fp,ra save/restore and use the stack frame the right
way!

llvm-svn: 39763
 2007-07-11 23:21:31 +00:00
Bruno Cardoso Lopes
0ba66ea1dc Now that stack is represented the right way, LOA starts at 0 
llvm-svn: 39761
 2007-07-11 23:17:41 +00:00
Bruno Cardoso Lopes
be14b3c16c Fixed AddLiveOut issues 
FI's created the write way to represent Mips stack

llvm-svn: 39760
 2007-07-11 23:16:16 +00:00
Bruno Cardoso Lopes
bc1b534410 Removed unused immediate PatLeaf, fixed lui instruction 
llvm-svn: 39759
 2007-07-11 22:47:02 +00:00
Bruno Cardoso Lopes
a851ed6989 Added MipsMachineFunction class, to hold Mips dinamic stack info when inserting Prologue/Epilog 
llvm-svn: 39758
 2007-07-11 22:44:21 +00:00
Lauro Ramos Venancio
18fc770fd0 Assert when TLS is not implemented. 
llvm-svn: 39737
 2007-07-11 17:19:51 +00:00
Chris Lattner
4810c53b05 The various "getModuleMatchQuality" implementations should return 
zero if they see a target triple they don't understand.

llvm-svn: 38463
 2007-07-09 17:25:29 +00:00
Bruno Cardoso Lopes
709699b8d3 Initial Mips support, here we go! =) 
- Modifications from the last patch included
  (issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.

llvm-svn: 37461
 2007-06-06 07:42:06 +00:00