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850 Commits

Author SHA1 Message Date
Akira Hatanaka
f71673c585 Make changes necessary in LowerFormalArguments to support Mips64. 
llvm-svn: 143218
 2011-10-28 19:55:48 +00:00
Akira Hatanaka
3069ec27da Make changes necessary in LowerCall to support Mips64. 
llvm-svn: 143217
 2011-10-28 19:49:00 +00:00
Akira Hatanaka
856f4e30b2 Add variable IsO32 to MipsTargetLowering. 
llvm-svn: 143213
 2011-10-28 18:47:24 +00:00
Bruno Cardoso Lopes
6a96a98825 Corrects previously incorrect $sp change in MipsCompilationCallback. 
The address for $sp, and addresses for sdc1/ldc1 must be 8-byte aligned

Patch by Petar Jovanovic.

llvm-svn: 142930
 2011-10-25 17:30:47 +00:00
Bruno Cardoso Lopes
edc2e30d42 Final patch that completes old JIT support for Mips: 
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

llvm-svn: 142378
 2011-10-18 17:50:36 +00:00
Bill Wendling
aea682a6fe Coding style cleanups. No functionality change. 
llvm-svn: 142341
 2011-10-18 07:40:22 +00:00
Eli Friedman
f43710f4a8 Fix misc warnings. Patch by Joe Abbey. 
llvm-svn: 142332
 2011-10-18 03:17:34 +00:00
Akira Hatanaka
4939842b5a Add definitions of conditional moves with 64-bit operands. Comment out code for 
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed. 

llvm-svn: 142226
 2011-10-17 18:53:29 +00:00
Akira Hatanaka
e8cb50da87 Move class and instruction definitions for conditional moves to a seperate file. 
llvm-svn: 142220
 2011-10-17 18:43:19 +00:00
Akira Hatanaka
9045499a59 Revert change made in r142205. 
llvm-svn: 142217
 2011-10-17 18:33:24 +00:00
Akira Hatanaka
0ab0d4d1f4 Redefine count-leading 0s and 1s instructions. 
llvm-svn: 142216
 2011-10-17 18:26:37 +00:00
Akira Hatanaka
f81b089ac3 Redefine mfhi/lo and mthi/lo instructions. 
llvm-svn: 142214
 2011-10-17 18:24:15 +00:00
Akira Hatanaka
4243d8876b Redefine multiply and divide instructions. 
llvm-svn: 142211
 2011-10-17 18:21:24 +00:00
Akira Hatanaka
6b17ee5b50 Add definition of a base class for logical shift/rotate instructions with two 
source registers and redefine 32-bit and 64-bit instructions.

llvm-svn: 142210
 2011-10-17 18:17:58 +00:00
Akira Hatanaka
3b8c93eda7 Add definition of a base class for logical shift/rotate immediate instructions 
and have 32-bit and 64-bit instructions derive from it.

llvm-svn: 142207
 2011-10-17 18:06:56 +00:00
Akira Hatanaka
82a1bab4ab Add definition of immZExt5_64 and redefine immZExt5 as an ImmLeaf. 
llvm-svn: 142205
 2011-10-17 18:01:00 +00:00
Akira Hatanaka
e4597ae8c1 Add f128 to datalayout string. 
llvm-svn: 141978
 2011-10-14 19:14:50 +00:00
Akira Hatanaka
70199b7136 Revert r141932, r141936 and r141937. 
llvm-svn: 141959
 2011-10-14 17:16:39 +00:00
Akira Hatanaka
24e913fbe2 Definition of function getMipsRegisterNumbering. 
Patch by Jack Carter and Reed Kotler at Mips. 

llvm-svn: 141938
 2011-10-14 03:04:24 +00:00
Akira Hatanaka
516b4b0352 Add definition of class MipsELFWriterInfo. 
Patch by Jack Carter and Reed Kotler at Mips. 

llvm-svn: 141937
 2011-10-14 02:55:47 +00:00
Akira Hatanaka
9922f8d014 Add missing relocation types. 
Patch by Jack Carter and Reed Kotler at Mips. 

llvm-svn: 141936
 2011-10-14 02:47:50 +00:00
Akira Hatanaka
b1ede8157d Fixup enumerations. 
Patch by Jack Carter at Mips. 

llvm-svn: 141934
 2011-10-14 02:38:56 +00:00
Akira Hatanaka
a5d655b991 Add more Mips relocation types. 
Patch by Jack Carter at Mips. 

llvm-svn: 141932
 2011-10-14 02:17:30 +00:00
Akira Hatanaka
68c6bb2c02 Define base class LogicNOR and make 32-bit and 64-bit NOR derive from it. 
llvm-svn: 141761
 2011-10-12 01:05:13 +00:00
Akira Hatanaka
08230e45e0 Fix encoding of 32-bit integer instructions. Change names of operands and nodes. 
Remove unused classes.

llvm-svn: 141757
 2011-10-12 00:56:06 +00:00
Akira Hatanaka
ab6aae33e9 Change name of class to ArithOverflowR. 
llvm-svn: 141743
 2011-10-11 23:43:48 +00:00
Akira Hatanaka
5273f6aabb Define class ArithLogicI. Make 32-bit and 64-bit arithmetic and logical 
instructions with two register operands derive from it.

llvm-svn: 141742
 2011-10-11 23:38:52 +00:00
Akira Hatanaka
0d687917ae Fix comment. 
llvm-svn: 141737
 2011-10-11 23:12:12 +00:00
Akira Hatanaka
12da673e60 Define classes ArithLogicR and ArithLogicOfR and make 32-bit and 64-bit 
arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.

llvm-svn: 141736
 2011-10-11 23:05:46 +00:00
Akira Hatanaka
8a43300a4f Fix function isUnalignedLoadStore. 
llvm-svn: 141722
 2011-10-11 22:04:01 +00:00
Akira Hatanaka
4ea17fffd6 Remove unused PatLeaf. 
llvm-svn: 141720
 2011-10-11 21:53:08 +00:00
Akira Hatanaka
99550c035f Change the names of 64-bit logical instructions so that they match the names of 
the real instructions.

llvm-svn: 141718
 2011-10-11 21:48:01 +00:00
Akira Hatanaka
7ae83fe86a Remove redundancy in setcc patterns using multiclass. 
llvm-svn: 141715
 2011-10-11 21:40:01 +00:00
Akira Hatanaka
f8aabd951e Use sltiu instead of sltu when a register operand and immediate are compared. 
llvm-svn: 141708
 2011-10-11 20:44:43 +00:00
Akira Hatanaka
27c0f84dce Add patterns for conditional branches with 64-bit register operands. 
llvm-svn: 141696
 2011-10-11 19:09:09 +00:00
Akira Hatanaka
1594be76f8 Add support for 64-bit set-on-less-than instructions. 
llvm-svn: 141695
 2011-10-11 18:53:46 +00:00
Akira Hatanaka
9df92e48e1 Add support for conditional branch instructions with 64-bit register operands. 
llvm-svn: 141694
 2011-10-11 18:49:17 +00:00
Akira Hatanaka
20808df5a0 Make changes necessary for supporting floating point load and store instructions 
that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.

llvm-svn: 141623
 2011-10-11 01:12:52 +00:00
Akira Hatanaka
3f89f9bc37 Modify lowering of GlobalAddress so that correct code is emitted when target is 
Mips64.

llvm-svn: 141618
 2011-10-11 00:55:05 +00:00
Akira Hatanaka
1913a9abc0 Modify MipsDAGToDAGISel::SelectAddr so that it can handle 64-bit pointers too. 
llvm-svn: 141615
 2011-10-11 00:44:20 +00:00
Akira Hatanaka
6f90f8d68d Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot. 
llvm-svn: 141613
 2011-10-11 00:37:28 +00:00
Akira Hatanaka
404fb72f59 Add definitions of 64-bit loads and stores. Add a patterns for unaligned 
zextloadi32 for which there is no corresponding pseudo or real instruction. 

llvm-svn: 141608
 2011-10-11 00:27:28 +00:00
Akira Hatanaka
ac95006d45 Change definitions of classes LoadM and StoreM in preparation for adding support 
for 64-bit load and store instructions. Add definitions of 64-bit memory operand
and 16-bit immediate operand.

llvm-svn: 141603
 2011-10-11 00:11:12 +00:00
Akira Hatanaka
4a78bb776f Simplify definition of FP move instructions. 
llvm-svn: 141476
 2011-10-08 03:50:18 +00:00
Akira Hatanaka
7780dcc74e Define classes and multiclasses for FP binary instructions. 
llvm-svn: 141475
 2011-10-08 03:38:41 +00:00
Akira Hatanaka
9595e84a11 Define multiclasses for FP-to-FP instructions. 
llvm-svn: 141474
 2011-10-08 03:29:22 +00:00
Akira Hatanaka
e39c39db4a Define classes for FP unary instructions and multiclasses for FP-to-fixed point 
conversion instructions. 

llvm-svn: 141473
 2011-10-08 03:19:38 +00:00
Akira Hatanaka
38d2ddcfac Add patterns for unaligned load and store instructions and enable the 
instruction selector to generate them.

llvm-svn: 141471
 2011-10-08 02:24:10 +00:00
Peter Collingbourne
253c6a3690 Build system infrastructure for multiple tblgens. 
llvm-svn: 141266
 2011-10-06 01:51:51 +00:00
Akira Hatanaka
28e360356f Fix assertion string. 
llvm-svn: 141197
 2011-10-05 18:17:49 +00:00