Arnold Schwaighofer
d47210011e
Added tail call optimization to the x86 back end. It can be
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enabled by passing -tailcallopt to llc. The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
elf/pic enabled + callee is in module + callee has
visibility protected or hidden
llvm-svn: 42870
2007-10-11 19:40:01 +00:00
Evan Cheng
9af50ee6ef
Commute x86 cmove instructions by swapping the operands and change the condition
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to its inverse.
Testing this as llcbeta
llvm-svn: 42661
2007-10-05 23:13:21 +00:00
Evan Cheng
b069dd6a25
Add support to convert more 64-bit instructions to 3-address instructions.
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llvm-svn: 42642
2007-10-05 18:20:36 +00:00
Evan Cheng
f658191412
ADC and SBB uses EFLAGS.
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llvm-svn: 42640
2007-10-05 17:59:57 +00:00
Evan Cheng
f3c130a8b6
Enabling new condition code modeling scheme.
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llvm-svn: 42459
2007-09-29 00:00:36 +00:00
Evan Cheng
826f0f94df
Doh. Calls clobber EFLAGS.
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llvm-svn: 42413
2007-09-27 19:01:55 +00:00
Evan Cheng
66eeb8440c
Some assemblers do not recognize aliases pushfd, pushfq, popfd, and popfq. Just emit them as pushf and popf.
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llvm-svn: 42371
2007-09-26 21:28:00 +00:00
Evan Cheng
37ee6eba29
Typos: POPQ -> POPFQ, POPD -> POPFD.
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llvm-svn: 42348
2007-09-26 06:38:29 +00:00
Evan Cheng
5cb9dbaaa1
Add pushf{d|q}, popf{d|q} to push and pop EFLAGS register.
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llvm-svn: 42335
2007-09-26 01:29:06 +00:00
Evan Cheng
36b3babfde
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after
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all the kinks are worked out.
llvm-svn: 42285
2007-09-25 01:57:46 +00:00
Dan Gohman
41a6dea029
Use xorl instead of xorq to enter a zero into a 64-bit register.
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llvm-svn: 42027
2007-09-17 14:55:08 +00:00
Dan Gohman
b9449c9118
Use "test reg,reg" in place of "cmp reg,0" for 64-bit operands. This was
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previously only done for 32-bit and smaller operands.
llvm-svn: 42024
2007-09-17 14:35:24 +00:00
Dan Gohman
df419c2b4f
Add patterns for SHLD64* and SHRD64*.
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llvm-svn: 41975
2007-09-14 23:17:45 +00:00
Evan Cheng
13797e4a74
Add implicit def of EFLAGS on those instructions that may modify flags.
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llvm-svn: 41962
2007-09-14 21:48:26 +00:00
Evan Cheng
b43255bc68
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
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llvm-svn: 41863
2007-09-11 19:55:27 +00:00
Dan Gohman
3bc1bc2590
Avoid storing and reloading zeros and other constants from stack slots
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by flagging the associated instructions as being trivially rematerializable.
llvm-svn: 41775
2007-09-07 21:32:51 +00:00
Evan Cheng
527fe7ab57
Mark load instructions with isLoad = 1.
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llvm-svn: 41595
2007-08-30 05:49:43 +00:00
Evan Cheng
69bbf3ed2a
Mac OS X X86-64 low 4G address not available.
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llvm-svn: 40702
2007-08-01 23:46:10 +00:00
Dan Gohman
e3464e6bec
Change the x86 assembly output to use tab characters to separate the
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mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.
llvm-svn: 40648
2007-07-31 20:11:57 +00:00
Evan Cheng
3493ec0ce1
Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load )
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llvm-svn: 40628
2007-07-31 08:04:03 +00:00
Christopher Lamb
919ce03da6
Change the x86 backend to use extract_subreg for truncation operations. Passes DejaGnu, SingleSource and MultiSource.
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llvm-svn: 40578
2007-07-29 01:24:57 +00:00
Bill Wendling
97342a9b0c
Add missing SSE builtins:
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__builtin_ia32_cvtss2si64
__builtin_ia32_cvttss2si64
__builtin_ia32_cvtsi642ss
__builtin_ia32_cvtsd2si64
__builtin_ia32_cvttsd2si64
__builtin_ia32_cvtsi642sd
llvm-svn: 40411
2007-07-23 03:07:27 +00:00
Evan Cheng
53cb03b583
No more noResults.
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llvm-svn: 40132
2007-07-21 00:34:19 +00:00
Evan Cheng
8312ed6f77
Change instruction description to split OperandList into OutOperandList and
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InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
Dan Gohman
bff1054303
Define the pushq instruction for x86-64.
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llvm-svn: 37625
2007-06-18 14:12:56 +00:00
Chris Lattner
307a29e831
add support for 128-bit integer add/sub
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llvm-svn: 37154
2007-05-17 06:35:11 +00:00
Bill Wendling
d380bc565b
Have MMX registers clobbered in x86-64 too.
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llvm-svn: 36494
2007-04-26 21:06:48 +00:00
Evan Cheng
32c45fa21e
Some AT&T syntax assembler (e.g. Mac OS X) does not recognize the movq alias for i64 <-> XMM moves.
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llvm-svn: 32609
2006-12-15 19:58:58 +00:00
Evan Cheng
5effab79f3
f64 <-> i64 bit_convert using movq in 64-bit mode.
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llvm-svn: 32587
2006-12-14 21:55:39 +00:00
Evan Cheng
4529b8cf2e
Fix a couple of typo's.
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llvm-svn: 32585
2006-12-14 19:46:06 +00:00
Evan Cheng
adeea85f7d
- Switch X86-64 JIT to large code size model.
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- Re-enable some codegen niceties for X86-64 static relocation model codegen.
- Clean ups, etc.
llvm-svn: 32238
2006-12-05 19:50:18 +00:00
Evan Cheng
2c35691a02
- Fix X86-64 JIT by temporarily disabling code that treats GV address as 32-bit
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immediate in small code model. The JIT cannot ensure GV's are placed in the
lower 4G.
- Some preliminary support for large code model.
llvm-svn: 32215
2006-12-05 04:01:03 +00:00
Evan Cheng
456101ebb9
- Use a different wrapper node for RIP-relative GV, etc.
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- Proper support for both small static and PIC modes under X86-64
- Some (non-optimal) support for medium modes.
llvm-svn: 32046
2006-11-30 21:55:46 +00:00
Evan Cheng
62d19fbf98
Fix JIT encoding bugs for shift / rotate by one ops.
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llvm-svn: 31952
2006-11-28 01:28:00 +00:00
Evan Cheng
fc1b3d8bc8
Correct instructions for moving data between GR64 and SSE registers; also correct load i64 / store i64 from v2i64.
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llvm-svn: 31795
2006-11-16 23:33:25 +00:00
Chris Lattner
7c265ad682
remove dead/redundant vars
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llvm-svn: 31435
2006-11-03 23:48:56 +00:00
Evan Cheng
ca66f49574
Add properties to ComplexPattern.
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llvm-svn: 30891
2006-10-11 21:03:53 +00:00
Evan Cheng
d22f3dd3ed
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
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llvm-svn: 30844
2006-10-09 20:57:25 +00:00
Evan Cheng
cfd7b147cf
X86ISD::CMP now produces a chain as well as a flag. Make that the chain
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operand of a conditional branch to allow load folding into CMP / TEST
instructions.
llvm-svn: 30241
2006-09-11 02:19:56 +00:00
Evan Cheng
100e48fe40
Remove TEST64mr. It's same as TEST64rm since and is commutative.
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llvm-svn: 30178
2006-09-08 06:56:55 +00:00
Evan Cheng
15dd42884e
Committing X86-64 support.
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llvm-svn: 30177
2006-09-08 06:48:29 +00:00