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c87ff88efb
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2987 Commits

Author SHA1 Message Date
Chris Lattner
c87ff88efb Add (untested) support for MULHS and MULHU. 
llvm-svn: 21107
 2005-04-06 04:21:07 +00:00
Chris Lattner
ba7cdbebb1 add signed versions of the extra precision multiplies 
llvm-svn: 21106
 2005-04-06 04:19:22 +00:00
Nate Begeman
aee0f81849 Turn off the div -> mul optimization until it works correctly 100% of the 
time.

llvm-svn: 21105
 2005-04-06 03:36:33 +00:00
Nate Begeman
b44597771c Add support for MULHS and MULHU nodes 
Have LegalizeDAG handle SREM and UREM for us
Codegen SDIV and UDIV by constant as a multiply by magic constant instead
of integer divide, which is very slow.

llvm-svn: 21104
 2005-04-06 00:25:27 +00:00
Andrew Lenharth
613a940af8 added lowerargs support for varargs 
llvm-svn: 21101
 2005-04-05 20:51:46 +00:00
Nate Begeman
82ff41c342 Behold, rlwinm with certain immediate arguments is printed as the much more 
readable slwi or srwi (shift left/right word immediate).

llvm-svn: 21099
 2005-04-05 18:19:50 +00:00
Nate Begeman
581553fd21 Fix cut & paste errors (32->64), and codegen float->int more optimally. 
llvm-svn: 21098
 2005-04-05 17:32:30 +00:00
Tanya Lattner
4d8f553a82 Updated to use dep analyzer. 
llvm-svn: 21097
 2005-04-05 16:36:44 +00:00
Nate Begeman
152dbbe856 Remove 64 bit simple ISel, it never worked correctly 
Add initial (buggy) implementation of 64 bit pattern ISel

llvm-svn: 21096
 2005-04-05 08:51:15 +00:00
Nate Begeman
a18a26f47c Back out the previous change to SelectBranchCC, since there are cases it 
could miscompile.  A correct solution will be found in the near future.

llvm-svn: 21095
 2005-04-05 04:32:16 +00:00
Nate Begeman
358dee806e Rename canUseAsImmediateForOpcode to getImmediateForOpcode to better 
indicate that it is not a boolean function.
Properly emit the pseudo instruction for conditional branch, so that we
  can fix up conditional branches whose displacements are too large.
Reserve the right amount of opcode space for said pseudo instructions.

llvm-svn: 21094
 2005-04-05 04:22:58 +00:00
Nate Begeman
ede4abc899 Implement SDIV by power of 2 as srawi/addze rather than load imm, divw 
llvm-svn: 21091
 2005-04-05 00:15:08 +00:00
Nate Begeman
00002553ba Pattern match fp mul-add, mul-sub, neg-mul-add, and neg-mul-sub 
llvm-svn: 21090
 2005-04-04 23:40:36 +00:00
Nate Begeman
682fd51f9c Add support for multiply-add, multiply-sub, and their negated versions 
llvm-svn: 21089
 2005-04-04 23:01:51 +00:00
Nate Begeman
d9af5c4fc5 Make sure that arg regs used by the call instruction are marked as such, so 
that regalloc doesn't cleverly reuse early arg regs loading later arg regs.
This fixes almost all outstanding failures in the pattern isel.

llvm-svn: 21086
 2005-04-04 22:17:48 +00:00
Nate Begeman
ce13bceb2a Remove unnecessary register copy now that regalloc is fixed 
llvm-svn: 21085
 2005-04-04 21:48:13 +00:00
Nate Begeman
bde3612ce3 i1 loads should also be from the low byte of the argument word. 
llvm-svn: 21077
 2005-04-04 09:09:00 +00:00
Nate Begeman
77427b1e77 Fix i64 return, fix CopyFromReg 
llvm-svn: 21076
 2005-04-04 06:52:38 +00:00
Duraid Madina
920aea2fa7 fix SREM/UREM, which gave incorrect results for x%y if x was zero. This is 
an ugly hack, but it seems to work. I should fix this properly and add a test
as well.

fixes multisource/obsequi (maybe others)

llvm-svn: 21075
 2005-04-04 05:05:52 +00:00
Duraid Madina
d896a18d33 add implicit use op 
llvm-svn: 21074
 2005-04-04 04:50:57 +00:00
Nate Begeman
b2e5a962ff Full varargs support. All of UnitTests now passes 
llvm-svn: 21070
 2005-04-03 23:11:17 +00:00
Nate Begeman
1a5aaf6009 Pass the correct value for the chain to the store 
llvm-svn: 21066
 2005-04-03 22:22:56 +00:00
Nate Begeman
82d17d0e70 Fix SHL_PARTS 
Start implementation of integer varargs

llvm-svn: 21065
 2005-04-03 22:13:27 +00:00
Andrew Lenharth
320fff1cbe is this simpler? I think it is simpler. 
llvm-svn: 21064
 2005-04-03 20:35:21 +00:00
Andrew Lenharth
4be5502eb4 fix 101 regressions 
llvm-svn: 21063
 2005-04-03 18:24:50 +00:00
Duraid Madina
bfbfb0e4c7 .bss is no problem here. 
llvm-svn: 21061
 2005-04-03 14:52:01 +00:00
Nate Begeman
127bd62534 Keeping up with the Joneses. 
Implement not, nor, nand, and eqv

llvm-svn: 21060
 2005-04-03 11:20:20 +00:00
Andrew Lenharth
c16ede8779 Select optimization 
llvm-svn: 21051
 2005-04-02 22:32:39 +00:00
Andrew Lenharth
bd19c1d25f Try several things. 1) drop /i from FP ops 2) factor out FP to Int moves and provide 21264 support for those 3) match not 4) match ornot andnot xornot 
llvm-svn: 21046
 2005-04-02 21:06:51 +00:00
Andrew Lenharth
08e5b4f996 FNEG/FABS/UNDEF 
llvm-svn: 21029
 2005-04-02 19:11:07 +00:00
Andrew Lenharth
04fd317736 FNEG/FABS 
llvm-svn: 21028
 2005-04-02 19:04:58 +00:00
Duraid Madina
63f75bdf49 ia64 asmprinter fixes: 
- turn off assembler's autoalignment
  - set FunctionAddrPrefix/Suffix so that .data8 entries pointing to
    functions have their value wrapped in @fptr(), so that a function
    descriptor will be materialized for that function.

llvm-svn: 21025
 2005-04-02 12:30:47 +00:00
Duraid Madina
5367cc3b49 support IDEF, fnegabs (thanks sampo) 
llvm-svn: 21023
 2005-04-02 10:33:53 +00:00
Duraid Madina
81675e4031 add fnegabs op 
llvm-svn: 21022
 2005-04-02 10:06:27 +00:00
Nate Begeman
402c04ff16 Set shift amount to Extend 
Implement ISD::FABS and ISD::FNEG nodes
Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS
Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions

llvm-svn: 21018
 2005-04-02 05:59:34 +00:00
Chris Lattner
8f30d63c1a add support for FABS and FNEG 
llvm-svn: 21015
 2005-04-02 05:30:17 +00:00
Duraid Madina
333132da85 add support FNEG and FABS 
llvm-svn: 21012
 2005-04-02 05:18:38 +00:00
Chris Lattner
a5d4718875 This target doesn't support fabs/fneg yet. 
llvm-svn: 21010
 2005-04-02 05:03:24 +00:00
Chris Lattner
71434aa2dd add an fabs instr 
llvm-svn: 21006
 2005-04-02 04:31:56 +00:00
Chris Lattner
8ee783d9f0 Add support for 64-bit shifts. 
llvm-svn: 21005
 2005-04-02 04:01:14 +00:00
Nate Begeman
8d60ca616f Fix i64 returns 
Generate PowerPC 'subfic' instruction when appropriate

llvm-svn: 20995
 2005-04-02 00:42:16 +00:00
Chris Lattner
67da3fdb70 Add support for ISD::UNDEF to the X86 be 
llvm-svn: 20990
 2005-04-01 22:46:45 +00:00
Nate Begeman
4034852ba9 Add ISD::UNDEF node 
Teach the SelectionDAG code how to expand and promote it
Have PPC32 LowerCallTo generate ISD::UNDEF for int arg regs used up by fp
  arguments, but not shadowing their value.  This allows us to do the right
  thing with both fixed and vararg floating point arguments.

llvm-svn: 20988
 2005-04-01 22:34:39 +00:00
Chris Lattner
375f5e6ed5 Fix another PATypeHolder error, contributed by Bill Wendling! 
llvm-svn: 20983
 2005-04-01 15:41:30 +00:00
Duraid Madina
48ef32d6d3 repair mindless SELECT waste. 
llvm-svn: 20982
 2005-04-01 10:35:00 +00:00
Nate Begeman
244b36582a Fix Olden/bh, CR0 was being set in the wrong order 
LowerCallTo and ISD::CALL are going to need to be modified, regs are being
set in the wrong order.

llvm-svn: 20981
 2005-04-01 08:57:43 +00:00
Nate Begeman
f3ead25b68 Also apply Chris's fix to FP select and SETCC 
llvm-svn: 20979
 2005-04-01 07:21:30 +00:00
Chris Lattner
0cd0036523 Move the selection of the arms of the select operation up to the conditional 
part to make sure we get the side effects and to avoid confusing the CFG.

llvm-svn: 20977
 2005-04-01 07:10:02 +00:00
Nate Begeman
e82a2d7373 Fix stores to global addresses 
Fix calls with no arguments

llvm-svn: 20975
 2005-04-01 05:57:17 +00:00
Nate Begeman
9d224ae29b Support indexed loads and stores. This drops Shootout/matrix time from 
18.8 to 14.8 seconds.  The Pattern ISel is now often faster than the
Simple ISel, esp. on memory intensive code.

llvm-svn: 20973
 2005-04-01 04:45:11 +00:00