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Commit Graph

130097 Commits

Author SHA1 Message Date
Richard Smith
c8f9cc971a Update and fix LLVM_ENABLE_MODULES:
1) We need to add this flag prior to adding any other, in case the user has
specified a -fmodule-cache-path= flag in their custom CXXFLAGS. Such a flag
causes -Werror builds to fail, and thus all config checks fail, until we add
the corresponding -fmodules flag. The modules selfhost bot does this, for
instance.

2) Delete module maps that were putting .cpp files into modules.

3) Enable -fmodules-local-submodule-visibility, to get proper module
visibility rules applied across submodules of the same module. Disable
-fmodules for C builds, since that flag is not available there.

llvm-svn: 266502
2016-04-16 00:48:58 +00:00
Richard Smith
0024f020dc Add some missing #includes, found by C++ modules selfhost.
llvm-svn: 266500
2016-04-16 00:42:37 +00:00
Duncan P. N. Exon Smith
0624b3edb7 Linker: Remove an unnecessary local variable in for loop, NFC
Reduces changes in a follow-up commit.

llvm-svn: 266493
2016-04-15 23:32:44 +00:00
Richard Smith
35752a052a Make this header include the header it depends on, rather than trying to include itself. Found by C++ modules build.
llvm-svn: 266492
2016-04-15 23:30:57 +00:00
Duncan P. N. Exon Smith
81ccdec56b ValueMapper: Hide Mapper::VM behind an accessor, NFC
Change Mapper::VM to a pointer and add a `getVM()` accessor for it.
While this has no functionality change, it minimizes the diff on an
upcoming patch that allows switching between instances of
ValueToValueMapTy on a single Mapper instance.

llvm-svn: 266490
2016-04-15 23:18:43 +00:00
Wei Mi
2936fb2655 Don't skip splitSeparateComponents in eliminateDeadDefs for HoistSpillHelper::hoistAllSpills.
Because HoistSpillHelper::hoistAllSpills is called in postOptimization, before the
patch we didn't want LiveRangeEdit::eliminateDeadDefs to call splitSeparateComponents
and generate unassigned new vregs. However, skipping splitSeparateComponents will make
verify-machineinstrs unhappy, so I remove the early return, and use
HoistSpillHelper::LRE_DidCloneVirtReg to assign physreg/stackslot for those new vregs.

In addition, some code reorganization to make class HoistSpillHelper privately inheriting
from LiveRangeEdit::Delegate possible. This is to be consistent with class RAGreedy and
class RegisterCoalescer.

Differential Revision: http://reviews.llvm.org/D19142

llvm-svn: 266489
2016-04-15 23:16:44 +00:00
Easwaran Raman
6e12136392 Add ProfileData to required_libraries
This should fix ppc64be build breakage due to r266477

llvm-svn: 266488
2016-04-15 23:08:52 +00:00
Evgeniy Stepanov
4c8a1f75c0 [cfi] Support explicit sections for functions in cfi-icall.
Allow explicit section for indirectly called functions in cfi-icall.
Jumptables for functions in the same type class must be contiguous, so they
always go to the default text section.

Fixes PR25079.

llvm-svn: 266486
2016-04-15 22:55:38 +00:00
Adrian Prantl
b940fef6b9 Convert this sample-based-profiling testcase to use a NoDebug CU.
llvm-svn: 266481
2016-04-15 22:05:38 +00:00
Kostya Serebryany
c84bd01bcd [libFuzzer] add a better warning for command line flags with -- (two dashes)
llvm-svn: 266480
2016-04-15 21:56:29 +00:00
Hans Wennborg
dc4376ad48 Switch lowering: don't add incoming PHI values from skipped bit test MBB's (PR27135)
After r245976, LLVM will skip the last bit test case if knows it will always be
true. However, we would still erroneously update PHI nodes with incoming values
from the MBB that would perform the final bit test, causing -verify-machineinstrs
to fail.

llvm-svn: 266479
2016-04-15 21:45:30 +00:00
Hans Wennborg
a332055ddf SelectionDAGISel: rangeify a loop
llvm-svn: 266478
2016-04-15 21:45:09 +00:00
Easwaran Raman
086e6e3f9e Replace the use of MaxFunctionCount module flag
Adds an interface to get ProfileSummary for a module and makes InlineCost use ProfileSummary to get max function count.

Differential Revision: http://reviews.llvm.org/D18622

llvm-svn: 266477
2016-04-15 21:39:58 +00:00
Kostya Serebryany
5c9ea3ceb9 [libFuzzer] menion the git mirror in the docs
llvm-svn: 266476
2016-04-15 21:10:27 +00:00
Vasileios Kalintiris
202510e60b [mips] More range-based for loops. NFC.
There are still a couple more inside the MIPS target. I opted for a single
commit in order to avoid spamming the list.

llvm-svn: 266472
2016-04-15 20:43:17 +00:00
Vasileios Kalintiris
820f0ffce2 [mips] Use range-based for loops and simplify slightly the code. NFC.
llvm-svn: 266471
2016-04-15 20:18:48 +00:00
Ulrich Weigand
41b710c861 [SystemZ] Call tryAddingSymbolicOperand in the disassembler
Use the tryAddingSymbolicOperand callback to attempt to present immediate
values in symbolic form when disassembling.  This is currently only used
for PC-relative immediates (which are most likely to be symbolic in the
SystemZ ISA).  Add new DecodeMethod types to allow distinguishing between
branch and non-branch instructions.

llvm-svn: 266469
2016-04-15 19:55:58 +00:00
Adrian Prantl
d83fea5735 Let the DISubprogram in this test point to the right compile unit.
llvm-svn: 266468
2016-04-15 19:38:14 +00:00
Adrian Prantl
45487c07fc Update testcase to new debug metadata format.
llvm-svn: 266467
2016-04-15 19:32:22 +00:00
Reid Kleckner
2dac2c60ff [codeview] Dump char16_t and char32_t simple types
llvm-svn: 266465
2016-04-15 18:26:45 +00:00
Tim Northover
4396c4b8cf ARM: don't try to hoist constant RHS out of a division.
Divisions by a constant can be converted into multiplies which are usually
cheaper, but this isn't possible if the constant gets separated (particularly
in loops). Fix this by telling ConstantHoisting that the immediate in a DIV is
cheap.

I considered making the check generic, but neither AArch64 (strangely) nor x86
showed any benefit on the tests I had.

llvm-svn: 266464
2016-04-15 18:17:18 +00:00
Chad Rosier
8ec20feca4 [AArch64] Add load/store pair instructions to getMemOpBaseRegImmOfsWidth().
This improves AA in the MI schduler when reason about paired instructions.

Phabricator Revision: http://reviews.llvm.org/D17098
PR26358

llvm-svn: 266462
2016-04-15 18:09:10 +00:00
Igor Kudrin
6d8bf78f13 Revert "[Coverage] Prevent detection of false instantiations in case of macro expansion."
This reverts commit r266436 as it broke buildbot.

llvm-svn: 266458
2016-04-15 17:53:48 +00:00
Davide Italiano
fbb720f29b [ParallelCG] Add a new splitCodeGen() API which takes a TargetMachineFactory.
This is a recommit of r266390 with a fix that will allow tests to pass
(hopefully). Before we got a StringRef to M->getTargetTriple() and right
after we moved the Module so we were referencing a dangling object.

llvm-svn: 266456
2016-04-15 17:34:32 +00:00
Marcin Koscielnicki
f442630636 [SystemZ] Fix large tests broken by conditional returns.
These were broken by D17339.

Differential Revision: http://reviews.llvm.org/D19158

llvm-svn: 266454
2016-04-15 17:24:40 +00:00
David Majnemer
77f3549d90 [InstCombine] Don't transform compares of calls to functions named fabs{f,l,}
InstCombine wants to optimize compares of calls to fabs with zero.
However, we didn't have the necessary legality checking to verify that
the function call had the same behavior as fabs.

llvm-svn: 266452
2016-04-15 17:21:03 +00:00
Geoff Berry
79ebd7fb73 Fix test to require Asserts since it uses debug output.
llvm-svn: 266448
2016-04-15 16:09:00 +00:00
Adrian Prantl
fb3abba237 [PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
Currently each Function points to a DISubprogram and DISubprogram has a
scope field. For member functions the scope is a DICompositeType. DIScopes
point to the DICompileUnit to facilitate type uniquing.

Distinct DISubprograms (with isDefinition: true) are not part of the type
hierarchy and cannot be uniqued. This change removes the subprograms
list from DICompileUnit and instead adds a pointer to the owning compile
unit to distinct DISubprograms. This would make it easy for ThinLTO to
strip unneeded DISubprograms and their transitively referenced debug info.

Motivation
----------

Materializing DISubprograms is currently the most expensive operation when
doing a ThinLTO build of clang.

We want the DISubprogram to be stored in a separate Bitcode block (or the
same block as the function body) so we can avoid having to expensively
deserialize all DISubprograms together with the global metadata. If a
function has been inlined into another subprogram we need to store a
reference the block containing the inlined subprogram.

Attached to https://llvm.org/bugs/show_bug.cgi?id=27284 is a python script
that updates LLVM IR testcases to the new format.

http://reviews.llvm.org/D19034
<rdar://problem/25256815>

llvm-svn: 266446
2016-04-15 15:57:41 +00:00
NAKAMURA Takumi
b397b15fe8 llvm/test/CodeGen/AArch64/arm64-csldst-mmo.ll requires +Asserts.
llvm-svn: 266443
2016-04-15 15:37:27 +00:00
Sanjay Patel
d65ab200a1 [SimplifyCFG] propagate branch metadata when creating select (PR27344)
This is almost identical to:
http://reviews.llvm.org/rL264527

This doesn't solve PR27344; it just allows the profile weights to survive. 
To solve the bug, we need to use the profile weights in the backend.

llvm-svn: 266442
2016-04-15 15:32:12 +00:00
NAKAMURA Takumi
d8734ae63f lli.cpp: Appease some builders. There might be ownership issues between LLVMContext and ExecutionEngine. Investigating.
llvm-svn: 266441
2016-04-15 15:31:28 +00:00
Geoff Berry
56afefb9c8 [AArch64] Add MMOs to callee-save load/store instructions.
Summary:
Without MMOs, the callee-save load/store instructions were treated as
volatile by the MI post-RA scheduler and AArch64LoadStoreOptimizer.

Reviewers: t.p.northover, mcrosier

Subscribers: aemerson, rengolin, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D17661

llvm-svn: 266439
2016-04-15 15:16:19 +00:00
Nirav Dave
a36a5aeca3 Fix typing on generated LXV2DX/STXV2DX instructions
[PPC] Previously when casting generic loads to LXV2DX/ST instructions we
would leave the original load return type in place allowing for an
assertion failure when we merge two equivalent LXV2DX nodes with
different types.

This fixes PR27350.

Reviewers: nemanjai

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D19133

llvm-svn: 266438
2016-04-15 15:01:38 +00:00
Jun Bum Lim
ad7ab4cf46 [MachineScheduler]Add support for store clustering
Perform store clustering just like load clustering. This change add
StoreClusterMutation in machine-scheduler. To control StoreClusterMutation,
added enableClusterStores() in TargetInstrInfo.h. This is enabled only on
AArch64 for now.

This change also add support for unscaled stores which were not handled in
getMemOpBaseRegImmOfs().

llvm-svn: 266437
2016-04-15 14:58:38 +00:00
Igor Kudrin
4f06b09bd9 [Coverage] Prevent detection of false instantiations in case of macro expansion.
The root of the problem was that findMainViewFileID(File, Function)
could return some ID for any given file, even though that file
was not the main file for that function.

This patch ensures that the result of this function is conformed
with the result of findMainViewFileID(Function).

Differential Revision: http://reviews.llvm.org/D18787

llvm-svn: 266436
2016-04-15 14:56:50 +00:00
Sanjay Patel
737ce217d1 [SimplifyCFG] add metadata to show failure to propagate (PR27344)
llvm-svn: 266435
2016-04-15 14:53:35 +00:00
Igor Kudrin
8c661fd7cc [Coverage] Add support for making test data for more than one function.
Differential Revision: http://reviews.llvm.org/D18758

llvm-svn: 266434
2016-04-15 14:46:31 +00:00
Nicolai Haehnle
730a184595 AMDGPU/SI: Fix regression with no-return atomics
Summary:
In the added test-case, the atomic instruction feeds into a non-machine
CopyToReg node which hasn't been selected yet, so guard against
non-machine opcodes here.

Reviewers: arsenm, tstellarAMD

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D19043

llvm-svn: 266433
2016-04-15 14:42:36 +00:00
Craig Topper
ab8ae0e21d Use MVT instead of EVT to remove a bunch of unnecessary calls to getSimpleVT.
llvm-svn: 266414
2016-04-15 06:20:21 +00:00
Craig Topper
d62db6aa41 Add a setOperationPromotedToType convenience method that sets an operation to promoted and set the type in one call. Use it so save code in X86.
llvm-svn: 266413
2016-04-15 06:20:18 +00:00
Craig Topper
31a58dd264 [X86] AND, OR, and XOR of vectors are always legal no need to set them legal explicitly.
llvm-svn: 266412
2016-04-15 06:20:14 +00:00
Craig Topper
61886cf59d [X86] Combine an if and else block that had the same set of calls to setOperationAction that only varied in Legal/Custom. Use the ternary operator on that argument instead. NFC
llvm-svn: 266410
2016-04-15 04:57:09 +00:00
Davide Italiano
b9715288e8 Revert "[LTO] Add a new splitCodeGen() API which takes a TargetMachineFactory."
This reverts commits r266390 and r266396 as they broke some bots.

llvm-svn: 266408
2016-04-15 02:07:03 +00:00
Justin Lebar
4b4ad39f81 [NVPTX] Set NVPTXTTI::getInliningThresholdMultiplier to 5.
Summary:
Calls on NVPTX are unusually expensive (for one thing, lots of state
needs to be saved to memory, which is slow), so make the inlininer much
more aggressive.

Reviewers: chandlerc

Subscribers: jholewinski, llvm-commits, tra

Differential Revision: http://reviews.llvm.org/D18561

llvm-svn: 266406
2016-04-15 01:38:50 +00:00
Justin Lebar
5824577459 [TTI] Add getInliningThresholdMultiplier.
Summary:
InlineCost's threshold is multiplied by this value.  This lets us adjust
the inlining threshold up or down on a per-target basis.  For example,
we might want to increase the threshold on targets where calls are
unusually expensive.

Reviewers: chandlerc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D18560

llvm-svn: 266405
2016-04-15 01:38:48 +00:00
Justin Lebar
9ca74f58f5 [ifcnv] Don't duplicate blocks that contain convergent instructions.
It's unsafe to duplicate blocks that contain convergent instructions
during ifcnv.  See the patch for details.

Reviewers: hfinkel

Differential Revision: http://reviews.llvm.org/D17518

llvm-svn: 266404
2016-04-15 01:38:41 +00:00
Justin Lebar
d4f9b5931f Move divergent-target test into CodeGen/NVPTX because it requires an NVPTX target.
llvm-svn: 266403
2016-04-15 01:20:52 +00:00
Justin Lebar
cad5d11faa [PM] Add a SpeculativeExecution pass for targets with divergent branches.
Summary:
This IR pass is helpful for GPUs, and other targets with divergent
branches.  It's a nop on targets without divergent branches.

Reviewers: chandlerc

Subscribers: llvm-commits, jingyue, rnk, joker.eph, tra

Differential Revision: http://reviews.llvm.org/D18626

llvm-svn: 266399
2016-04-15 00:32:12 +00:00
Justin Lebar
c6bd85bac2 [Speculation] Add a SpeculativeExecution mode where the pass does nothing unless TTI::hasBranchDivergence() is true.
Summary:
This lets us add this pass to the IR pass manager unconditionally; it
will simply not do anything on targets without branch divergence.

Reviewers: tra

Subscribers: llvm-commits, jingyue, rnk, chandlerc

Differential Revision: http://reviews.llvm.org/D18625

llvm-svn: 266398
2016-04-15 00:32:09 +00:00
Davide Italiano
919373bcbd [ParallelCG] Attempt to placate MSVC.
llvm-svn: 266396
2016-04-15 00:25:19 +00:00