Evan Cheng
7fffe3cf58
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
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llvm-svn: 115008
2010-09-29 00:27:46 +00:00
Evan Cheng
39c462b4f1
Add support to model pipeline bypass / forwarding.
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llvm-svn: 115005
2010-09-28 23:50:49 +00:00
Evan Cheng
2279dc1d2a
Remove a unused instruction itinerary class.
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llvm-svn: 114782
2010-09-25 01:06:02 +00:00
Evan Cheng
64a24ab747
Fix zero and sign extension instructions scheduling itineraries.
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llvm-svn: 114780
2010-09-25 00:49:35 +00:00
Evan Cheng
124ae30ef8
More pseudo instruction scheduling itinerary fixes.
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llvm-svn: 114768
2010-09-24 22:41:41 +00:00
Evan Cheng
b79a03a3ca
For each instruction itinerary class, specify the number of micro-ops each
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instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.
This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.
llvm-svn: 113513
2010-09-09 18:18:55 +00:00
Jim Grosbach
f3bd81ce11
Clean up 80 column violations. No functional change.
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llvm-svn: 105350
2010-06-02 21:53:11 +00:00
Anton Korobeynikov
e325c693a5
Make processor FUs unique for given itinerary. This extends the limit of 32
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FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.
llvm-svn: 101754
2010-04-18 20:31:01 +00:00
David Goodwin
6b56e77397
Add ARMv6 itineraries.
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llvm-svn: 89218
2009-11-18 18:39:57 +00:00
David Goodwin
1d72b88015
Checkpoint NEON scheduling itineraries.
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llvm-svn: 82657
2009-09-23 21:38:08 +00:00
David Goodwin
0db84be1dc
Add Cortex-A8 VFP model.
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llvm-svn: 82483
2009-09-21 20:52:17 +00:00
David Goodwin
d57f44783c
Update Cortex-A8 instruction itineraries for integer instructions.
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llvm-svn: 79436
2009-08-19 18:00:44 +00:00
Evan Cheng
9d351a7246
Turn on if-conversion for thumb2.
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llvm-svn: 79084
2009-08-15 07:59:10 +00:00
David Goodwin
dd797db6bd
Finalize itineraries for cortex-a8 integer multiply
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llvm-svn: 78908
2009-08-13 15:51:13 +00:00
David Goodwin
2686178489
Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter.
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llvm-svn: 78736
2009-08-11 22:38:43 +00:00
David Goodwin
b2f53ed68a
Checkpoint scheduling itinerary changes.
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llvm-svn: 78564
2009-08-10 15:56:13 +00:00
Evan Cheng
149b0d4cf1
Fix comment.
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llvm-svn: 76693
2009-07-21 23:54:22 +00:00
Evan Cheng
f671ce4eba
Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits.
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llvm-svn: 73747
2009-06-19 01:51:50 +00:00
