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Commit Graph

79561 Commits

Author SHA1 Message Date
Eli Bendersky
2545105c90 Remove trailing spaces
llvm-svn: 148654
2012-01-22 09:02:48 +00:00
Eli Bendersky
d2042f3698 Basic runtime dynamic loading capabilities added to ELFObjectFile, implemented
in a subclass named DyldELFObject. This class supports rebasing the object file
it represents by re-mapping section addresses to the actual memory addresses
the object was placed in. This is required for MC-JIT implementation on ELF with
debugging support.

Patch reviewed on llvm-commits.

Developed together with Ashok Thirumurthi and Andrew Kaylor.

llvm-svn: 148653
2012-01-22 09:01:03 +00:00
Eli Bendersky
1fa68fd976 Split the lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h header to smaller logical headers.
ELF and MachO implementations of RuntimeDyldImpl go into their own header files now.

Reviewed on llvm-commits

llvm-svn: 148652
2012-01-22 07:05:02 +00:00
Craig Topper
5e9b6de71f Make code a little less verbose.
llvm-svn: 148651
2012-01-22 03:07:48 +00:00
David Blaikie
05fe2f515d Help GCC along with code that's actually unreachable.
Unfortunately I don't think there's a fix for this that will work upstream and
also satisfy Clang's -Wunreachable-code, which is a pity. But I'll give it some
more thought -perhaps there's some way out.

llvm-svn: 148645
2012-01-22 01:17:04 +00:00
Craig Topper
eaca0c20ea Remove unused X86 ISD node type defines.
llvm-svn: 148644
2012-01-22 01:15:56 +00:00
Craig Topper
bb07c0da2d Move some vector shift patterns into their instruction definitions.
llvm-svn: 148643
2012-01-22 00:41:20 +00:00
Craig Topper
63c59673a3 Add memory patterns for some of the fp<->integer conversion instructions. Fold some patterns into instruction definitions.
llvm-svn: 148641
2012-01-21 18:37:15 +00:00
David Blaikie
93fafabfea Remove unreachable defaults from gtest.
This will ensure LLVM and Clang build -Wswitch-enum-redundant-default (an on-by-default warning I'm about to add to Clang).

llvm-svn: 148639
2012-01-21 18:02:01 +00:00
Benjamin Kramer
bdd152e9cf Remove unused variables.
llvm-svn: 148635
2012-01-21 10:42:44 +00:00
Craig Topper
d493ca92c4 Fix PR11819 introduced by r148537. I'd commit the test case, but the generated code is terrible as it gets fully scalarized. Expect a future commit to fix that.
llvm-svn: 148632
2012-01-21 08:49:33 +00:00
Evan Cheng
7bd1a126ed Fix an obvious typo.
llvm-svn: 148622
2012-01-21 03:31:03 +00:00
Jakob Stoklund Olesen
46feaf86cf Handle register masks in LiveVariables.
A register mask operand kills any live physreg that isn't preserved.
Unlike an implicit-def operand, the clobbered physregs are never live
afterwards.

This means LiveVariables has to track a much smaller number of live
physregs, and it should spend much less time in addRegisterDead().

llvm-svn: 148609
2012-01-21 00:58:53 +00:00
Jim Grosbach
e6dc36349b RuntimeDyld alignment adjustment from MachO file.
The MachO file stores section alignment as log2(alignment-in-bytes). The
allocation routines want the raw alignment-in-bytes value, so adjust
for that.

llvm-svn: 148604
2012-01-21 00:21:53 +00:00
Jim Grosbach
5100c10a17 Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction.
llvm-svn: 148601
2012-01-21 00:07:56 +00:00
Jakob Stoklund Olesen
0eca627fb7 Delete an unused member variable.
llvm-svn: 148594
2012-01-20 22:48:59 +00:00
Jim Grosbach
472cca5206 Fix inverted condition.
llvm-svn: 148593
2012-01-20 22:44:03 +00:00
Devang Patel
0ecda3fc14 Intel syntax: Robustify register parsing.
llvm-svn: 148591
2012-01-20 22:32:05 +00:00
Jakob Stoklund Olesen
85cd4626f4 Support register masks in MachineLICM.
Only PostRA LICM is affected.

llvm-svn: 148589
2012-01-20 22:27:12 +00:00
Jakob Stoklund Olesen
704b3cf1d2 Handle register masks in DeadMachineInstructionElim.
Don't track live physregs that are clobbered by a register mask operand.

llvm-svn: 148588
2012-01-20 22:27:09 +00:00
David Blaikie
06ecc99a56 More dead code removal (using -Wunreachable-code)
llvm-svn: 148578
2012-01-20 21:51:11 +00:00
Andrew Trick
207780ec8e Handle a corner case with IV chain collection with bailout instead of assert.
Fixes PR11783: bad cast to AddRecExpr.

llvm-svn: 148572
2012-01-20 21:23:40 +00:00
Andrew Trick
343a9ff799 Test case comments missing from my previous checkin.
llvm-svn: 148571
2012-01-20 21:21:27 +00:00
Devang Patel
0638a44a24 Intel syntax: Parse ... PTR [-8]
llvm-svn: 148570
2012-01-20 21:21:01 +00:00
Devang Patel
e836c95860 Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.
llvm-svn: 148569
2012-01-20 21:14:06 +00:00
Bob Wilson
793fa215cb ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651>
We have patterns for vector sext and zext operations but were missing
anyext.  Without those patterns, codegen will fail when the selection DAG
has any_extend nodes.

llvm-svn: 148568
2012-01-20 20:59:56 +00:00
Jim Grosbach
2b1f17ec6e TblGen diagnostic for mismatched template instantiation.
Providing a template argment to a non-templatized class was crashing
tblgen. Add a diagnostic.

For example,
$ cat bug.td
class A;

def B : A<0> {
}
$ llvm-tblgen bug.td
bug.td:3:11: error: template argument provided to non-template class
def B : A<0> {
          ^

llvm-svn: 148565
2012-01-20 20:02:39 +00:00
Jim Grosbach
b6e177bd4e VST2 four-register w/ update pseudos for fixed/register update.
rdar://10724489

llvm-svn: 148560
2012-01-20 19:16:00 +00:00
Jim Grosbach
4579f05f36 NEON use vmov.i32 to splat some f32 values into vectors.
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.

rdar://10616677

llvm-svn: 148556
2012-01-20 18:09:51 +00:00
Benjamin Kramer
a55074eb7f Don't use my favorite C++11 feature (comma at end of enum).
llvm-svn: 148555
2012-01-20 18:08:30 +00:00
Kostya Serebryany
b37a1263e1 Extend Attributes to 64 bits
Problem: LLVM needs more function attributes than currently available (32 bits).
One such proposed attribute is "address_safety", which shows that a function is being checked for address safety (by AddressSanitizer, SAFECode, etc).

Solution:
- extend the Attributes from 32 bits to 64-bits
- wrap the object into a class so that unsigned is never erroneously used instead
- change "unsigned" to "Attributes" throughout the code, including one place in clang.
- the class has no "operator uint64 ()", but it has "uint64_t Raw() " to support packing/unpacking.
- the class has "safe operator bool()" to support the common idiom:  if (Attributes attr = getAttrs()) useAttrs(attr);
- The CTOR from uint64_t is marked explicit, so I had to add a few explicit CTOR calls
- Add the new attribute "address_safety". Doing it in the same commit to check that attributes beyond first 32 bits actually work.
- Some of the functions from the Attribute namespace are worth moving inside the class, but I'd prefer to have it as a separate commit.

Tested:
"make check" on Linux (32-bit and 64-bit) and Mac (10.6)
built/run spec CPU 2006 on Linux with clang -O2.


This change will break clang build in lib/CodeGen/CGCall.cpp.
The following patch will fix it.

llvm-svn: 148553
2012-01-20 17:56:17 +00:00
Benjamin Kramer
14636e5e0a Protect SmallVectorImpl's constructor and a few other methods that aren't meant to be public.
llvm-svn: 148550
2012-01-20 16:39:46 +00:00
Benjamin Kramer
320f5ae35d Add missing breaks to switch.
Found by the clang static analyzer.

llvm-svn: 148543
2012-01-20 14:42:37 +00:00
Benjamin Kramer
fe9eb0e6e8 Remove a bunch of unused variable assignments.
Found by the clang static analyzer.

llvm-svn: 148541
2012-01-20 14:42:32 +00:00
Benjamin Kramer
1d768583f5 Remove obviously invalid early exit that prevented analyzing ConstantAggregateZeros.
Found by the clang static analyzer.

llvm-svn: 148540
2012-01-20 14:42:25 +00:00
Rafael Espindola
cd18a7720d Don't use -fvisibility-inlines-hidden on mingw to try to avoid a lot of
warnings from gcc.

llvm-svn: 148539
2012-01-20 13:10:10 +00:00
Craig Topper
7b50829b7f Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. As long as only a single lane of the source is used in the lane in the destination. This makes the splitting match much closer to what happens with 256-bit shuffles when AVX is disabled and only 128-bit XMM is allowed.
llvm-svn: 148537
2012-01-20 09:29:03 +00:00
Nick Lewycky
55814f0b32 Fix CountCodeReductionForAlloca to more accurately represent what SROA can and
can't handle. Also don't produce non-zero results for things which won't be
transformed by SROA at all just because we saw the loads/stores before we saw
the use of the address.

llvm-svn: 148536
2012-01-20 08:35:20 +00:00
Andrew Trick
be3e9530e1 SCEVExpander fixes. Affects LSR and indvars.
LSR has gradually been improved to more aggressively reuse existing code, particularly existing phi cycles. This exposed problems with the SCEVExpander's sloppy treatment of its insertion point. I applied some rigor to the insertion point problem that will hopefully avoid an endless bug cycle in this area. Changes:

- Always used properlyDominates to check safe code hoisting.

- The insertion point provided to SCEV is now considered a lower bound. This is usually a block terminator or the use itself. Under no cirumstance may SCEVExpander insert below this point.

- LSR is reponsible for finding a "canonical" insertion point across expansion of different expressions.

- Robust logic to determine whether IV increments are in "expanded" form and/or can be safely hoisted above some insertion point.

Fixes PR11783: SCEVExpander assert.

llvm-svn: 148535
2012-01-20 07:41:13 +00:00
Craig Topper
e2d3f3060d Add support for selecting 256-bit PALIGNR.
llvm-svn: 148532
2012-01-20 05:53:00 +00:00
Rafael Espindola
5af87be2ba cmake: pass -fvisibility-inlines-hidden if it is supported. In a
Release+Asserts build with -DBUILD_SHARED_LIBS=ON, the install
directory goes from 72MB to 70MB.

llvm-svn: 148530
2012-01-20 04:07:48 +00:00
Eli Friedman
d13443515e Remove a low-quality test which was failing on Windows; test/CodeGen/X86/sret.ll is a better test for the relevant behavior.
llvm-svn: 148526
2012-01-20 02:06:40 +00:00
Bill Wendling
f599e9d12a When lowering the 'resume' instruction, look to see if we can eliminate the
'insertvalue' instructions that recreate the structure returned by the
'landingpad' instruction. Because the 'insertvalue' instruction isn't supported
by FastISel, this can save a bit of time during -O0 compilation.

llvm-svn: 148520
2012-01-20 00:53:28 +00:00
Eli Friedman
ffa3b8b5f1 Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff.
llvm-svn: 148513
2012-01-20 00:05:46 +00:00
Chad Rosier
ce02cd3faa Fix typo.
llvm-svn: 148497
2012-01-19 21:50:08 +00:00
Benjamin Kramer
b3479ef519 Silence warnings about mixing enums.
llvm-svn: 148495
2012-01-19 21:11:13 +00:00
Owen Anderson
989d05dfdb Add a dump() implementation for sub-instruction MCOperands.
llvm-svn: 148493
2012-01-19 19:32:20 +00:00
Owen Anderson
61bdf3c55c Add a new form of MCOperand, for representing sub-instructions. This is intended for supporting bundles through the MC layer, rather than lowering them pre-MC as we currently do for Thumb2 IT blocks. Since these sub-instruction operands hold pointers to the sub-instructions, it is the responsibility of the target's AsmPrinter to provide storage for them for the duration of the EmitInstruction() call.
llvm-svn: 148492
2012-01-19 19:24:37 +00:00
Dan Gohman
9bb84ffb6c Set the "tail" flag on pattern-matched objc_storeStrong calls.
rdar://10531041.

llvm-svn: 148490
2012-01-19 19:14:36 +00:00
Devang Patel
b42cea31aa Post process 'and', 'sub' instructions and select better encoding, if available.
llvm-svn: 148489
2012-01-19 18:40:55 +00:00