1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 12:02:58 +02:00
Commit Graph

166 Commits

Author SHA1 Message Date
Jyotsna Verma
d2eb3f84fd Add constant extender support to GP-relative load/store instructions.
llvm-svn: 170672
2012-12-20 06:52:46 +00:00
Jyotsna Verma
cb321ae6c7 Add TSFlags to ALU32 type instructions for constant-extender/Relationship maps.
llvm-svn: 170671
2012-12-20 06:45:39 +00:00
Bill Wendling
56d9c4b832 Rename the 'Attributes' class to 'Attribute'. It's going to represent a single attribute in the future.
llvm-svn: 170502
2012-12-19 07:18:57 +00:00
Jyotsna Verma
7fb1e065a0 Use multiclass for new-value store instructions with MEMri operand.
llvm-svn: 169814
2012-12-11 05:12:25 +00:00
NAKAMURA Takumi
10a9cdfc27 [CMake] Update dependencies to intrinsics_gen corresponding to r169711.
llvm-svn: 169724
2012-12-10 05:27:15 +00:00
Matthew Curtis
596e698b79 In hexagon convertToHardwareLoop, don't deref end() iterator
In particular, check if MachineBasicBlock::iterator is end() before
using it to call getDebugLoc();

See also this thread on llvm-commits:
   http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121112/155914.html

llvm-svn: 169634
2012-12-07 21:03:15 +00:00
Jyotsna Verma
9995a62d05 Define new-value store instructions with base+immediate addressing mode
using multiclass.

llvm-svn: 169432
2012-12-05 22:02:56 +00:00
Jyotsna Verma
c8d145f6f6 Use multiclass to define store instructions with base+immediate offset
addressing mode and immediate stored value.

llvm-svn: 169408
2012-12-05 19:32:03 +00:00
Matthew Curtis
67b48517cb Fix misplaced closing brace.
llvm-svn: 169404
2012-12-05 19:00:34 +00:00
Jyotsna Verma
52d66f1d1e Define store instructions with base+register offset addressing mode
using multiclass.

llvm-svn: 169314
2012-12-04 21:58:25 +00:00
Jyotsna Verma
ec3f676ca1 Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count trailing/leading zeros)
instructions.

llvm-svn: 169287
2012-12-04 18:05:01 +00:00
Jyotsna Verma
0dd9064b5a Add constant extender support to ALU32 instructions for V2.
llvm-svn: 169284
2012-12-04 17:12:00 +00:00
Chandler Carruth
a98c778194 Sort includes for all of the .h files under the 'lib' tree. These were
missed in the first pass because the script didn't yet handle include
guards.

Note that the script is now able to handle all of these headers without
manual edits. =]

llvm-svn: 169224
2012-12-04 07:12:27 +00:00
Jyotsna Verma
2878599f9d Move all operand definitions into HexagonOperands.td
llvm-svn: 169213
2012-12-04 05:00:31 +00:00
Jyotsna Verma
5743b854a0 Move generic Hexagon subtarget information into Hexagon.td
llvm-svn: 169212
2012-12-04 04:29:16 +00:00
Jyotsna Verma
e17db34a1c Define store instructions with base+immediate offset addressing mode
using multiclass.

llvm-svn: 169168
2012-12-03 22:26:28 +00:00
Jyotsna Verma
3bea2435da Define load instructions with base+immediate offset addressing mode
using multiclass.

llvm-svn: 169153
2012-12-03 21:13:13 +00:00
Jyotsna Verma
a762d2c7c0 Define unsigned const-ext predicates.
llvm-svn: 169149
2012-12-03 20:39:45 +00:00
Jyotsna Verma
c9aa3a1e1b Removing unnecessary 'else' statement from the predicates defined in HexagonOperards.td.
llvm-svn: 169148
2012-12-03 20:14:38 +00:00
Chandler Carruth
a490793037 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131
2012-12-03 16:50:05 +00:00
Jyotsna Verma
deb06efce6 Define signed const-ext predicates.
llvm-svn: 169117
2012-12-03 06:54:50 +00:00
Jyotsna Verma
7b9aa748cb Use multiclass for the load instructions with MEMri operand.
llvm-svn: 169018
2012-11-30 17:31:52 +00:00
Jyotsna Verma
9baa0ebf94 Use multiclass for the store instructions with MEMri operand.
llvm-svn: 168983
2012-11-30 06:10:22 +00:00
Jyotsna Verma
9ec526d755 Use multiclass for the load instructions with 'base + register offset'
addressing mode.

llvm-svn: 168976
2012-11-30 04:19:09 +00:00
Jyotsna Verma
7806a44024 Use multiclass for 'transfer' instructions.
llvm-svn: 168929
2012-11-29 19:35:44 +00:00
Jyotsna Verma
f5ca442d79 Define signed const-ext immediate operands and their predicates.
llvm-svn: 168810
2012-11-28 20:58:14 +00:00
Jyotsna Verma
cac9f4bdf8 Fix comments in HexagonOperands.td.
llvm-svn: 168617
2012-11-26 21:56:51 +00:00
Jyotsna Verma
57c7894ac6 Add new predicates for the immediate operands.
llvm-svn: 168451
2012-11-21 20:05:09 +00:00
Jyotsna Verma
ccd944029e Use one common 'let' expression to set PrintMethod for all immediate operands.
llvm-svn: 168449
2012-11-21 19:53:42 +00:00
Rafael Espindola
eeea053b3e Finish the renaming.
llvm-svn: 168437
2012-11-21 16:56:33 +00:00
Jyotsna Verma
79da647716 Renamed HexagonImmediates.td -> HexagonOperands.td.
llvm-svn: 168434
2012-11-21 16:28:18 +00:00
Jyotsna Verma
5aa884e1c7 Removing some unused instruction definitions from the Hexagon backend.
llvm-svn: 168388
2012-11-20 22:14:23 +00:00
Jyotsna Verma
a472ef54f3 Added multiclass for post-increment load instructions.
llvm-svn: 167974
2012-11-14 20:38:48 +00:00
Jyotsna Verma
195fdd718c Test commit.
Add a blank line.

llvm-svn: 167819
2012-11-13 06:31:55 +00:00
Andrew Trick
76ebc86f9a ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.
This is in preparation for adding "weak" DAG edges, but generally
simplifies the design.

llvm-svn: 167435
2012-11-06 03:13:46 +00:00
Pranav Bhandarkar
c796c7d713 Use the relationship models infrastructure to add two relations - getPredOpcode
and getPredNewOpcode. The first relates non predicated instructions with their
predicated forms and the second relates predicated instructions with their
predicate-new forms.

Patch by Jyotsna Verma!

llvm-svn: 167243
2012-11-01 19:13:23 +00:00
Nadav Rotem
4a918454d8 Implement a basic VectorTargetTransformInfo interface to be used by the loop and bb vectorizers for modeling the cost of instructions.
llvm-svn: 166593
2012-10-24 17:22:41 +00:00
Nadav Rotem
3cce3abf28 Reapply the TargerTransformInfo changes, minus the changes to LSR and Lowerinvoke.
llvm-svn: 166248
2012-10-18 23:22:48 +00:00
Bob Wilson
b6adb70bdd Temporarily revert the TargetTransform changes.
The TargetTransform changes are breaking LTO bootstraps of clang.  I am
working with Nadav to figure out the problem, but I am reverting it for now
to get our buildbots working.

This reverts svn commits: 165665 165669 165670 165786 165787 165997
and I have also reverted clang svn 165741

llvm-svn: 166168
2012-10-18 05:43:52 +00:00
Nadav Rotem
b82a3821f7 Add a new interface to allow IR-level passes to access codegen-specific information.
llvm-svn: 165665
2012-10-10 22:04:55 +00:00
Andrew Trick
4ca94d939c misched: Use the TargetSchedModel interface wherever possible.
Allows the new machine model to be used for NumMicroOps and OutputLatency.

Allows the HazardRecognizer to be disabled along with itineraries.

llvm-svn: 165603
2012-10-10 05:43:09 +00:00
Bill Wendling
b53357de39 Create enums for the different attributes.
We use the enums to query whether an Attributes object has that attribute. The
opaque layer is responsible for knowing where that specific attribute is stored.

llvm-svn: 165488
2012-10-09 07:45:08 +00:00
Micah Villmow
bb1a25cd67 Move TargetData to DataLayout.
llvm-svn: 165402
2012-10-08 16:38:25 +00:00
Bill Wendling
3535cd36c8 Use new accessor methods to query for attributes.
llvm-svn: 165205
2012-10-04 06:43:21 +00:00
Sebastian Pop
270e075dec TargetLowering interface to set/get minimum block entries for jump tables.
Provide interface in TargetLowering to set or get the minimum number of basic
blocks whereby jump tables are generated for switch statements rather than an
if sequence.

    getMinimumJumpTableEntries() defaults to 4.
    setMinimumJumpTableEntries() allows target configuration.

    This patch changes the default for the Hexagon architecture to 5
    as it improves performance on some benchmarks.

llvm-svn: 164628
2012-09-25 20:35:36 +00:00
Sergei Larin
3c6b1bfa42 DAG post-process for Hexagon MI scheduler
This patch introduces a possibility for Hexagon MI scheduler
to perform some target specific post- processing on the scheduling
DAG prior to scheduling.

llvm-svn: 163903
2012-09-14 15:07:59 +00:00
Benjamin Kramer
36c359546f Remove redundant private field.
clang warned about this being unused in Release builds.

llvm-svn: 163899
2012-09-14 12:19:58 +00:00
Andrew Trick
ffec33601b Reorganize MachineScheduler interfaces and publish them in the header.
The Hexagon target decided to use a lot of functionality from the
target-independent scheduler. That's fine, and other targets should be
able to do the same. This reorg and API update makes that easy.

For the record, ScheduleDAGMI was not meant to be subclassed. Instead,
new scheduling algorithms should be able to implement
MachineSchedStrategy and be done. But if need be, it's nice to be
able to extend ScheduleDAGMI, so I also made that easier. The target
scheduler is somewhat more apt to break that way though.

llvm-svn: 163580
2012-09-11 00:39:15 +00:00
Sergei Larin
adf81918db Add "blocked" heuristic to the Hexagon MI scheduler.
Improve AQ instruction selection in the Hexagon MI scheduler.

llvm-svn: 163523
2012-09-10 17:31:34 +00:00
Benjamin Kramer
f7e00de5d0 Fix alignment of .comm and .lcomm on mingw32.
For some reason .lcomm uses byte alignment and .comm log2 alignment so we can't
use the same setting for both. Fix this by reintroducing the LCOMM enum.
I verified this against mingw's gcc.

llvm-svn: 163420
2012-09-07 21:08:01 +00:00