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604 Commits

Author SHA1 Message Date
Dan Gohman
74fa421281 Re-enable elimination of unnecessary SUBREG_TO_REG instructions in 
LowerSubregs, and fix an x86-64 isel bug that this exposed.

SUBREG_TO_REG for x86-64 implicit zero extension is only safe for
isel to generate when the source is known to always have zeros in
the high 32 bits. The EXTRACT_SUBREG instruction does not clear
the high 32 bits.

llvm-svn: 54444
 2008-08-07 02:54:50 +00:00
Dan Gohman
1674a7c2f3 Add an extra example that shouldn't get an and instruction. 
llvm-svn: 54443
 2008-08-07 02:23:06 +00:00
Dan Gohman
cc784f1662 Re-introduce the 8-bit subreg zext-inreg patterns for x86-32, 
this time using MOV32to32_ and MOV16to16_. Thanks to Evan for
suggesting this.

llvm-svn: 54418
 2008-08-06 18:27:21 +00:00
Evan Cheng
f4d1119fbd Fix PR2620: Fix X86cmppd selection code so it expects operands to be v2f64. 
llvm-svn: 54376
 2008-08-05 22:19:15 +00:00
Evan Cheng
a07795a0c3 Fix PR2596: out of bound reference. 
llvm-svn: 54375
 2008-08-05 21:51:46 +00:00
Owen Anderson
d1185e4da3 Update the remaining tests not to use -disable-correct-folding, and remove two 
that couldn't be updated.

llvm-svn: 54359
 2008-08-05 18:19:14 +00:00
Owen Anderson
117b0e405d One more -disable-correct-folding case removed. 
llvm-svn: 54358
 2008-08-05 18:08:56 +00:00
Owen Anderson
c5fd801d85 Remove another -disable-correct-folding use. 
llvm-svn: 54357
 2008-08-05 18:05:58 +00:00
Owen Anderson
f845ea8d52 Eliminate another use of -disable-correct-folding. 
llvm-svn: 54356
 2008-08-05 18:03:01 +00:00
Evan Cheng
754148a2ec Fix PR2568: Fix bug that cause redudant kill marker after its live interval has been extended due to coalescing. 
llvm-svn: 54346
 2008-08-05 07:10:38 +00:00
Owen Anderson
231111faf9 Update these tests to work by disabling the new correct CFG generation. This flag should ONLY be used to for tests like these. 
llvm-svn: 54334
 2008-08-04 23:55:29 +00:00
Dan Gohman
60ea311ec8 Fix SDISel lowering of PHI nodes to use ComputeValueVTs. 
This allows it to work correctly on aggregate values.
This fixes PR2623.

llvm-svn: 54331
 2008-08-04 23:42:46 +00:00
Dale Johannesen
c1ae4b8c08 Make sse2 explicit, for non-x86 hosts. 
llvm-svn: 54251
 2008-07-31 20:16:33 +00:00
Dan Gohman
f691fc703d Improve dagcombining for sext-loads and sext-in-reg nodes. 
llvm-svn: 54239
 2008-07-31 00:50:31 +00:00
Dan Gohman
6f3fa16fd9 I missed this file in r54223. movzbl is now used instead 
of movzbw here.

llvm-svn: 54224
 2008-07-30 18:23:34 +00:00
Dan Gohman
efb5d2ce6e Reapply r54147 with a constraint to only use the 8-bit 
subreg form on x86-64, to avoid the problem with x86-32
having GPRs that don't have 8-bit subregs.

Also, change several 16-bit instructions to use 
equivalent 32-bit instructions. These have a smaller
encoding and avoid partial-register updates.

llvm-svn: 54223
 2008-07-30 18:09:17 +00:00
Mon P Wang
fb483982f5 Added support for overloading intrinsics (atomics) based on pointers 
to different address spaces.  This alters the naming scheme for those
intrinsics, e.g., atomic.load.add.i32 => atomic.load.add.i32.p0i32

llvm-svn: 54195
 2008-07-30 04:36:53 +00:00
Dan Gohman
ebe629a4b2 Revert 54147. 
llvm-svn: 54148
 2008-07-29 01:02:18 +00:00
Dan Gohman
1816900fd1 Add x86 isel patterns to match what would be a ZERO_EXTEND_INREG operation, 
which is represented in codegen as an 'and' operation. This matches them
with movz instructions, instead of leaving them to be matched by and
instructions with an immediate field.

llvm-svn: 54147
 2008-07-28 22:18:25 +00:00
Dan Gohman
a5a50a8853 Fix embedded CRLF characters. 
llvm-svn: 54125
 2008-07-27 18:37:58 +00:00
Nate Begeman
1396e3d206 Fix test RUN line 
llvm-svn: 54040
 2008-07-25 19:08:59 +00:00
Nate Begeman
5523d40e4b Disable mov{L, LP, HP, HLP, *DUP} shuffles for mmx 
mmx needs its own fancy shuffle logic based on unpack; for now we get correct but awful code.

Also commit Mon Ping's VSETCC patch

llvm-svn: 54039
 2008-07-25 19:05:58 +00:00
Dan Gohman
6d394147f2 This test needs -aggressive-remat enabled. 
llvm-svn: 54015
 2008-07-25 15:25:32 +00:00
Dan Gohman
680e1bd958 Enable rematerialization of constants using AliasAnalysis::pointsToConstantMemory, 
and knowledge of PseudoSourceValues. This unfortunately isn't sufficient to allow
constants to be rematerialized in PIC mode -- the extra indirection is a
complication.

llvm-svn: 54000
 2008-07-25 00:02:30 +00:00
Dan Gohman
da5c2b50b8 Add target triples so these tests behave as expected on non-darwin hosts. 
llvm-svn: 53991
 2008-07-24 18:08:01 +00:00
Evan Cheng
055f5e6ed0 New test case. 
llvm-svn: 53971
 2008-07-24 00:22:05 +00:00
Evan Cheng
20c9cdbe69 Fix PR2485: do all 4-element SSE shuffles in max. of 2 shuffle instructions. 
Based on patch by Nicolas Capens.

llvm-svn: 53939
 2008-07-23 00:22:17 +00:00
Duncan Sands
550e0de239 LegalizeTypes support for VSETCC. Fixes PR2575. 
llvm-svn: 53938
 2008-07-22 23:54:03 +00:00
Evan Cheng
1aa928a8e6 Fix pr2566: incorrect assumption about bit_convert. It doesn't not have to output a vector value. Patch by Nicolas Capens! 
llvm-svn: 53932
 2008-07-22 20:42:56 +00:00
Evan Cheng
901d469e05 Fix PR2574: implement v2f32 scalar_to_vector. 
llvm-svn: 53927
 2008-07-22 18:39:19 +00:00
Bill Wendling
98b6e63176 Fix for first part of PR2562. Generate the "pinsrw" instruction for inserts 
into v4i16 vectors.

llvm-svn: 53807
 2008-07-20 02:32:23 +00:00
Anton Korobeynikov
6f354293fe Testcase for PR2549 
llvm-svn: 53785
 2008-07-19 06:31:12 +00:00
Evan Cheng
d26080487b Subreg live interval valno may not have a corresponding def machineinstr since it's less precise. 
llvm-svn: 53734
 2008-07-17 19:48:53 +00:00
Evan Cheng
48b2f3dfe9 Add nounwind. 
llvm-svn: 53733
 2008-07-17 19:48:04 +00:00
Evan Cheng
05e5317cab Fix PR2536: a nasty spiller bug. If a two-address instruction uses a register but the use portion of its live range is not part of its liveinterval, it must be defined by an implicit_def. In that case, do not spill the use. e.g. 
8   %reg1024<def> = IMPLICIT_DEF
12  %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2

The live range [12, 14) are not part of the r1024 live interval since it's defined by an implicit def. It will not conflicts with live interval of r1025. Now suppose both registers are spilled, you can easily see a situation where both registers are reloaded before the INSERT_SUBREG and both target registers that would overlap.

llvm-svn: 53503
 2008-07-12 01:56:02 +00:00
Duncan Sands
52f1dbf139 Port a shift-by-1 optimization from LegalizeDAG: it 
was presumably added after the rest of the code was
copied to LegalizeTypes.

llvm-svn: 53459
 2008-07-11 16:54:57 +00:00
Bill Wendling
9f17caa9a9 The frame address on an x86-64 box needs to be offset by -8, not -4. 
llvm-svn: 53450
 2008-07-11 07:18:52 +00:00
Evan Cheng
02a618dc56 Fix for PR2472. Use movss to set lower 32-bits of a zero XMM vector. 
llvm-svn: 53386
 2008-07-10 01:08:23 +00:00
Anton Korobeynikov
f710ada483 Testcase for PR2024 
llvm-svn: 53327
 2008-07-09 14:09:41 +00:00
Evan Cheng
cf3a4ad46d Fix two serious LSR bugs. 
1. LSR runOnLoop is always returning false regardless if any transformation is made.
2. AddUsersIfInteresting can create new instructions that are added to DeadInsts. But there is a later early exit which prevents them from being freed.

llvm-svn: 53193
 2008-07-07 19:51:32 +00:00
Dale Johannesen
51edab312c Considering predecessors of exit blocks gets 
us a little more tail merging.

llvm-svn: 52986
 2008-07-01 21:50:49 +00:00
Chris Lattner
153b6695b8 test doesn't need eh info 
llvm-svn: 52811
 2008-06-27 03:14:20 +00:00
Dale Johannesen
76f5dc0cc4 Allow for rounding up of stack frame. 
llvm-svn: 52751
 2008-06-26 01:55:32 +00:00
Chris Lattner
2b67ff8632 when we know the signbit of an input to uint_to_fp is zero, 
change it to sint_to_fp on targets where that is cheaper (and
visaversa of course).  This allows us to compile uint_to_fp to:

_test:
	movl	4(%esp), %eax
	shrl	$23, %eax
	cvtsi2ss	%eax, %xmm0
	movl	8(%esp), %eax
	movss	%xmm0, (%eax)
	ret

instead of:

	.align	3
LCPI1_0:					##  double
	.long	0	## double least significant word 4.5036e+15
	.long	1127219200	## double most significant word 4.5036e+15
	.text
	.align	4,0x90
	.globl	_test
_test:
	subl	$12, %esp
	movl	16(%esp), %eax
	shrl	$23, %eax
	movl	%eax, (%esp)
	movl	$1127219200, 4(%esp)
	movsd	(%esp), %xmm0
	subsd	LCPI1_0, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movl	20(%esp), %eax
	movss	%xmm0, (%eax)
	addl	$12, %esp
	ret

llvm-svn: 52747
 2008-06-26 00:16:49 +00:00
Evan Cheng
71fbfe73c1 - Fix a x86 vector isel bug: illegal transformation of a vector_shuffle into a 
shift.
- Add a readme entry for a missing vector_shuffle optimization that results in
  awful codegen.

llvm-svn: 52740
 2008-06-25 20:52:59 +00:00
Mon P Wang
7d89d61387 Added MemOperands to Atomic operations since Atomics touches memory. 
Added abstract class MemSDNode for any Node that have an associated MemOperand
Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and
atomic.lss => atomic.load.sub

llvm-svn: 52706
 2008-06-25 08:15:39 +00:00
Evan Cheng
bab5925a0b Enable two-address remat by default. 
llvm-svn: 52701
 2008-06-25 01:16:38 +00:00
Dale Johannesen
244433ebb1 v2f32 is now a valid (MMX) type which breaks this 
test (doesn't work for any MMX vector types, it's
not me).  Rewritten to use v2i16 which is generic
and going to stay that way; I think that preserves
the point of the test.

llvm-svn: 52692
 2008-06-24 22:03:36 +00:00
Evan Cheng
a62f5f0f82 If it's determined safe, remat MOV32r0 (i.e. xor r, r) and others as it is instead of using the longer MOV32ri instruction. 
llvm-svn: 52670
 2008-06-24 07:10:51 +00:00
Bill Wendling
d6b7d457cf Make test work on non-x86 machines (like my G4 PPC). 
llvm-svn: 52619
 2008-06-23 06:16:31 +00:00