Dan Gohman
cba99ee717
Fix live-out reg logic to not insert over-aggressive AssertZExt
...
instructions. This fixes lua.
llvm-svn: 68083
2009-03-31 01:38:29 +00:00
Evan Cheng
d7824e208a
Turn a 2-address instruction into a 3-address one when it's profitable even if the two-address operand is killed.
...
e.g.
%reg1024<def> = MOV r1
%reg1025<def> = ADD %reg1024, %reg1026
r0 = MOV %reg1025
If it's not possible / profitable to commute ADD, then turning ADD into a LEA saves a copy.
llvm-svn: 68065
2009-03-30 21:34:07 +00:00
Bill Wendling
76042faa52
Balance out quote in debug output.
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llvm-svn: 68059
2009-03-30 20:32:22 +00:00
Bill Wendling
3b2cea6ef5
Fix grammar-o in comment.
...
llvm-svn: 68057
2009-03-30 20:30:02 +00:00
Dan Gohman
abcfb30fc2
Constify arguments in isSuccessor and isLayoutSuccessor.
...
llvm-svn: 68054
2009-03-30 20:06:29 +00:00
Duncan Sands
602234cdf3
Fix PR3899: add support for extracting floats from vectors
...
when using -soft-float.
Based on a patch by Jakob Stoklund Olesen.
llvm-svn: 67996
2009-03-29 13:51:06 +00:00
Arnold Schwaighofer
76188bc8a1
Make check in CheckTailCallReturnConstraints for ignorable instructions between
...
a CALL and a RET node more generic. Add a test for tail calls with a void
return.
llvm-svn: 67943
2009-03-28 12:36:29 +00:00
Arnold Schwaighofer
636127325b
Enable tail call optimization for functions that return a struct (bug 3664) and for functions that return types that need extending (e.g i1).
...
llvm-svn: 67934
2009-03-28 08:33:27 +00:00
Evan Cheng
a15fdaa292
Optimize some 64-bit multiplication by constants into two lea's or one lea + shl since imulq is slow (latency 5). e.g.
...
x * 40
=>
shlq $3, %rdi
leaq (%rdi,%rdi,4), %rax
This has the added benefit of allowing more multiply to be folded into addressing mode. e.g.
a * 24 + b
=>
leaq (%rdi,%rdi,2), %rax
leaq (%rsi,%rax,8), %rax
llvm-svn: 67917
2009-03-28 05:57:29 +00:00
Dan Gohman
b360b0390a
Fix what surely must be a copy+pasto.
...
llvm-svn: 67881
2009-03-27 23:55:04 +00:00
Dan Gohman
401df03e2d
Initialize LiveOutInfo's APInt members to zero, as APInt's
...
default constructor produces an uninitialized APInt.
This fixes PR3896.
llvm-svn: 67879
2009-03-27 23:51:02 +00:00
John Mosby
67ffa789e8
Shrink wrapping in PEI: initial release. Finishing development, enable with --shrink-wrap.
...
llvm-svn: 67828
2009-03-27 06:09:40 +00:00
Owen Anderson
2312267684
Don't assign a new stack slot if the pre-alloc splitter already assigned one.
...
llvm-svn: 67764
2009-03-26 18:53:38 +00:00
Bill Wendling
f4247ff478
Pull transform from target-dependent code into target-independent code.
...
llvm-svn: 67742
2009-03-26 06:14:09 +00:00
Evan Cheng
7e4217176a
Revert 67132. This is breaking some objective-c apps.
...
Also fixes SDISel so it *does not* force promote return value if the function is not marked signext / zeroext.
llvm-svn: 67701
2009-03-25 20:20:11 +00:00
Dale Johannesen
9fb1dcd077
When optimizing with debug info, don't keep the
...
stoppoint nodes around until Legalize; doing this
imposed an ordering on a sequence of loads that
came from different lines, interfering with scheduling.
llvm-svn: 67692
2009-03-25 17:36:08 +00:00
Evan Cheng
3a7489a4cc
CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.
...
llvm-svn: 67668
2009-03-25 01:47:28 +00:00
Devang Patel
225831fc9e
Do not ignore DW_TAG_class_type!
...
llvm-svn: 67661
2009-03-25 00:28:40 +00:00
Evan Cheng
758c95f07a
Fix PR3845: Avoid stale MachineInstruction pointer reference.
...
llvm-svn: 67649
2009-03-24 20:33:17 +00:00
Chris Lattner
135eeefe66
more tidying: name the components of PhysReg in the case when
...
the target constraint specifies a specific physreg.
llvm-svn: 67618
2009-03-24 15:27:37 +00:00
Chris Lattner
8793e812ef
Tidy a bit more.
...
llvm-svn: 67617
2009-03-24 15:25:07 +00:00
Chris Lattner
a60dd19c3e
simplify this code a bit now that "allocation to a vreg class" can never
...
fail.
llvm-svn: 67616
2009-03-24 15:22:11 +00:00
Dan Gohman
547cfc882e
Minor compile-time optimization; don't bother checking
...
canClobberPhysRegDefs if the successor node doesn't
clobber any physical registers.
llvm-svn: 67587
2009-03-24 00:50:07 +00:00
Dan Gohman
e6d7478bc1
Add a pre-pass to the burr-list scheduler which makes adjustments to
...
help out the register pressure reduction heuristics in the case of
nodes with multiple uses. Currently this uses very conservative
heuristics, so it doesn't have a broad impact, but in cases where it
does help it can make a big difference.
llvm-svn: 67586
2009-03-24 00:49:12 +00:00
Evan Cheng
b3196f1298
Do not emit comments unless -asm-verbose.
...
llvm-svn: 67580
2009-03-24 00:17:40 +00:00
Evan Cheng
702a8b4399
Fix a bug in spill weight computation. If the alias is a super-register, and the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases.
...
e.g. allocating for GR32, bh is not used, updating bl spill weight.
bl should get the same spill weight otherwise it will be choosen
as a spill candidate since spilling bh doesn't make ebx available.
This fix PR2866.
llvm-svn: 67574
2009-03-23 22:57:19 +00:00
Dale Johannesen
34123aba43
Fix internal representation of fp80 to be the
...
same as a normal i80 {low64, high16} rather
than its own {high64, low16}. A depressing number
of places know about this; I think I got them all.
Bitcode readers and writers convert back to the old
form to avoid breaking compatibility.
llvm-svn: 67562
2009-03-23 21:16:53 +00:00
Dan Gohman
60c652de57
When unfolding a load during scheduling, the new operator node has
...
a data dependency on the load node, so it really needs a
data-dependence edge to the load node, even if the load previously
existed.
And add a few comments.
llvm-svn: 67554
2009-03-23 20:20:43 +00:00
Evan Cheng
7e4a6972d6
Fix PR3391 and PR3864. Reg allocator infinite looping.
...
llvm-svn: 67544
2009-03-23 18:24:37 +00:00
Dan Gohman
a6842708e6
Don't set SUnit::hasPhysRegDefs to true unless the defs are
...
actually have uses, which reflects the way it's used.
llvm-svn: 67540
2009-03-23 17:39:36 +00:00
Dan Gohman
b6b24c5fc1
Fix canClobberPhysRegDefs to check all SDNodes grouped together
...
in an SUnit, instead of just the first one. This fix is needed
by some upcoming scheduler changes.
llvm-svn: 67531
2009-03-23 16:23:01 +00:00
Dan Gohman
78a1698ac0
Add a new bit to SUnit to record whether a node has implicit physreg
...
defs, regardless of whether they are actually used.
llvm-svn: 67528
2009-03-23 16:10:52 +00:00
Dan Gohman
18daca0895
Now that errs() is properly non-buffered, there's no need to
...
explicitly flush it.
llvm-svn: 67526
2009-03-23 15:57:19 +00:00
Evan Cheng
2ec94dd447
Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies.
...
llvm-svn: 67512
2009-03-23 08:01:15 +00:00
Evan Cheng
4b11d96b62
Do not fold away subreg_to_reg if the source register has a sub-register index. That means the source register is taking a sub-register of a larger register. e.g. On x86
...
%RAX<def> = ...
%RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
The first def is defining RAX, not EAX so the top bits were not zero-extended.
llvm-svn: 67511
2009-03-23 07:19:58 +00:00
Dan Gohman
60cfa194d4
Simplify this code; use a while instead of an if and a do-while.
...
llvm-svn: 67400
2009-03-20 20:42:23 +00:00
Evan Cheng
0c629db2aa
For inline asm output operand that matches an input. Encode the input operand index in the high bits.
...
llvm-svn: 67387
2009-03-20 18:03:34 +00:00
Sanjiv Gupta
15d6146126
Fixed build warnings for unused variables.
...
llvm-svn: 67372
2009-03-20 13:49:20 +00:00
Sanjiv Gupta
5957bb99ba
Fixed the comment. No functionality change.
...
llvm-svn: 67370
2009-03-20 09:38:50 +00:00
Chris Lattner
b18e8617be
Apply the patch requested in PR3846.
...
llvm-svn: 67364
2009-03-20 05:08:24 +00:00
Sebastian Redl
e4e5b1c2f2
Fix the Win32 VS2008 build:
...
- Make type declarations match the struct/class keyword of the definition.
- Move AddSignalHandler into the namespace where it belongs.
- Correctly call functions from template base.
- Some other small changes.
With this patch, LLVM and Clang should build properly and with far less noise under VS2008.
llvm-svn: 67347
2009-03-19 23:26:52 +00:00
Evan Cheng
f47c144bff
Added MachineInstr::isRegTiedToDefOperand to check for two-addressness.
...
llvm-svn: 67335
2009-03-19 20:30:06 +00:00
Chris Lattner
3181caa065
Fix PEI to not walk off the start of a block when an updated instruction
...
is the first in its block. This is PR3842.
llvm-svn: 67304
2009-03-19 17:15:43 +00:00
Mon P Wang
3d7fb6738a
Added missing support for widening when splitting an unary op (PR3683)
...
and expanding a bit convert (PR3711). In both cases, we extract the
valid part of the widen vector and then do the conversion.
llvm-svn: 67175
2009-03-18 06:24:04 +00:00
Rafael Espindola
6a6d9e48dd
Don't force promotion of return arguments on the callee.
...
Some architectures (like x86) don't require it.
This fixes bug 3779.
llvm-svn: 67132
2009-03-17 23:43:59 +00:00
Chris Lattner
e3c442050d
Fix codegen to compute the size of an allocation by multiplying the
...
size by the array amount as an i32 value instead of promoting from
i32 to i64 then doing the multiply. Not doing this broke wrap-around
assumptions that the optimizers (validly) made. The ultimate real
fix for this is to introduce i64 version of alloca and remove mallocinst.
This fixes PR3829
llvm-svn: 67093
2009-03-17 19:36:00 +00:00
Sanjiv Gupta
390dd214db
r66870 missed this out.
...
llvm-svn: 67082
2009-03-17 15:46:15 +00:00
Duncan Sands
34e7f207ee
Reapply r67049, with the test adjusted for darwin
...
(which produces "call L_f$stub" rather than "call f").
llvm-svn: 67079
2009-03-17 09:46:22 +00:00
Mon P Wang
7184e30bdb
Fix a problem with DAGCombine where we were building an illegal build
...
vector shuffle mask. Forced the mask to be built using i32. Note: this will
be irrelevant once vector_shuffle no longer takes a build vector for the
shuffle mask.
llvm-svn: 67076
2009-03-17 06:33:10 +00:00
Evan Cheng
0dccb325d1
Spiller may unfold load / mod / store instructions as an optimization when the would be loaded value is available in a register. It needs to check if it's legal to clobber the register. Also, the register can contain values of multiple spill slots, make sure to check all instead of just the one being unfolded.
...
llvm-svn: 67068
2009-03-17 01:23:09 +00:00