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18 Commits

Author SHA1 Message Date
Chris Lattner
fa884ac11b Rename some subtarget features. A CPU now can *have* 64-bit instructions, 
can in 32-bit mode we can choose to optionally *use* 64-bit registers.

llvm-svn: 28824
 2006-06-16 17:34:12 +00:00
Evan Cheng
667b133ab9 getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. 
llvm-svn: 28378
 2006-05-18 00:12:58 +00:00
Evan Cheng
ea24815aa3 Remove PointerType from class Target 
llvm-svn: 28368
 2006-05-17 21:20:27 +00:00
Chris Lattner
661ee5d3c1 add callee saved vector regs 
llvm-svn: 26805
 2006-03-16 22:07:06 +00:00
Chris Lattner
ba10d4e4ab Mark instructions that are cracked by the PPC970 decoder as such. 
llvm-svn: 26720
 2006-03-13 05:15:10 +00:00
Chris Lattner
a278639f29 Several big changes: 
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
   type instead of a table in the .cpp file.  Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
   algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
   accurately.

llvm-svn: 26719
 2006-03-12 09:13:49 +00:00
Chris Lattner
9f70a7924d Add a subtarget feature for the stfiwx instruction. I know the G5 has it, 
but I don't know what other PPC impls do.  If someone could update the proc
table, I would appreciate it :)

llvm-svn: 26421
 2006-02-28 07:08:22 +00:00
Evan Cheng
77885c204d Subtarget feature can now set any variable to any value 
llvm-svn: 25678
 2006-01-27 08:09:42 +00:00
Jim Laskey
22e578cd95 Add attribute name and type to SubtargetFeatures. 
llvm-svn: 24012
 2005-10-26 17:28:23 +00:00
Chris Lattner
a14bcc1e4c mark this as beta 
llvm-svn: 23906
 2005-10-23 22:23:45 +00:00
Chris Lattner
1e815394b4 rearrange things a bit so that instructions can use subtarget features in the 
future.

llvm-svn: 23902
 2005-10-23 22:08:13 +00:00
Chris Lattner
baa3ca710e improve -help output 
llvm-svn: 23892
 2005-10-23 05:28:51 +00:00
Jim Laskey
12484c7699 Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's 
to group appropriately and provide cues to maintainers that the lists don't
need to be ordered.

llvm-svn: 23880
 2005-10-22 08:04:24 +00:00
Chris Lattner
f6b98c786e 64-bit reg support should not be enabled by default, as support isn't complete. 
llvm-svn: 23878
 2005-10-21 22:15:43 +00:00
Jim Laskey
1fbdee408d Plugin new subtarget backend into the build. 
llvm-svn: 23870
 2005-10-21 19:05:19 +00:00
Jim Laskey
514a74d946 Added InstrSchedClass to each of the PowerPC Instructions. 
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.

llvm-svn: 23830
 2005-10-19 19:51:16 +00:00
Chris Lattner
11127fcf98 Rename PowerPC*.td -> PPC*.td 
llvm-svn: 23740
 2005-10-14 23:40:39 +00:00
Chris Lattner
612940b7b0 Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td 
llvm-svn: 23738
 2005-10-14 23:37:35 +00:00