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160 Commits

Author SHA1 Message Date
Dan Gohman
9cbc3fb1ab Revert the earlier change that removed the M_REMATERIALIZABLE machine 
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728
 2007-06-26 00:48:07 +00:00
Dan Gohman
b60d8a92c9 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad 
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
 2007-06-19 01:48:05 +00:00
Evan Cheng
12b3002673 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. 
llvm-svn: 37643
 2007-06-19 01:26:51 +00:00
Evan Cheng
1be50b2f54 Add clobbersPred - instruction that clobbers condition code / register which are used to predicate instructions. 
llvm-svn: 37465
 2007-06-06 10:14:55 +00:00
Evan Cheng
ecb8e3dc44 Rename M_PREDICATED to M_PREDICABLE; opcode can be specified isPredicable without having a PredicateOperand. 
llvm-svn: 37116
 2007-05-16 20:45:24 +00:00
Evan Cheng
34ce8e7297 Mark all (not just the first) predicate operand M_PREDICATE_OPERAND. 
llvm-svn: 37061
 2007-05-15 01:20:36 +00:00
Evan Cheng
a54c20ca4e Recognize target instruction flag 'isReMaterializable'. 
llvm-svn: 35159
 2007-03-19 06:20:37 +00:00
Jim Laskey
1bab68f592 Files missing from LABEL check in. 
llvm-svn: 33539
 2007-01-26 17:29:20 +00:00
Bill Wendling
f13d78d3b8 What should be the last unnecessary <iostream>s in the library. 
llvm-svn: 32333
 2006-12-07 22:21:48 +00:00
Evan Cheng
e1ca976ce4 Add opcode to TargetInstrDescriptor. 
llvm-svn: 31804
 2006-11-17 01:46:27 +00:00
Chris Lattner
efcd65f335 ADd support for adding constraints to suboperands 
llvm-svn: 31748
 2006-11-15 02:38:17 +00:00
Chris Lattner
6836cbaf9d allow ptr_rc to explicitly appear in an instructions operand list, it doesn't 
have to be a subpart of a complex operand.

llvm-svn: 31618
 2006-11-10 02:01:40 +00:00
Evan Cheng
8743c67826 Remove M_2_ADDR_FLAG. 
llvm-svn: 31583
 2006-11-09 02:22:54 +00:00
Chris Lattner
908ea22022 Mark predicate operands as such in operand info. 
llvm-svn: 31483
 2006-11-06 23:53:31 +00:00
Chris Lattner
e1960fc065 simplify the way operand flags and constraints are handled, making it easier 
to extend.

llvm-svn: 31481
 2006-11-06 23:49:51 +00:00
Chris Lattner
04b6336b73 recognize ppc's blr instruction as predicated 
llvm-svn: 31480
 2006-11-06 21:44:54 +00:00
Evan Cheng
8e65006b5e Clean up some code. 
llvm-svn: 31451
 2006-11-04 09:40:23 +00:00
Evan Cheng
c566892bd5 Add operand constraints to TargetInstrInfo. 
llvm-svn: 31333
 2006-11-01 00:27:05 +00:00
Jim Laskey
085a8477a7 Eliminate data relocations by using NULL instead of global empty list. 
llvm-svn: 29250
 2006-07-21 21:15:20 +00:00
Jim Laskey
a67adda697 Use an enumeration to eliminate data relocations. 
llvm-svn: 29249
 2006-07-21 20:57:35 +00:00
Evan Cheng
07d8ccec50 Instructions with variable operands (variable_ops) can have a number required 
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
                "call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.

Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.

llvm-svn: 28791
 2006-06-15 07:22:16 +00:00
Evan Cheng
00c1318055 lib/Target/Target.td 
llvm-svn: 28386
 2006-05-18 20:42:07 +00:00
Evan Cheng
409dd126bf Noop instruction 
llvm-svn: 28241
 2006-05-12 07:47:00 +00:00
Evan Cheng
ca3dc213dc Set isStore of instructions with ISD::TRUNCSTORE root node. 
llvm-svn: 28075
 2006-05-03 02:08:34 +00:00
Chris Lattner
8cbad2f76a Put instruction names into the first non TargetInstrInfo namespace found. 
llvm-svn: 28043
 2006-05-01 23:46:16 +00:00
Evan Cheng
0bae850dda Formating 
llvm-svn: 28036
 2006-05-01 09:30:17 +00:00
Evan Cheng
efcb0061df Mark instructions whose pattern is (store ...) isStore. 
llvm-svn: 28032
 2006-05-01 09:04:20 +00:00
Chris Lattner
56e4ca77c6 Don't fill in fields that no longer exist. 
llvm-svn: 27898
 2006-04-20 18:32:22 +00:00
Chris Lattner
c3d295a47c If we want to emit things in enum order, use getInstructionsByEnumValue to 
get the order, don't compute it ourselves.

Don't emit stuff like (14<<0), emit 14 instead.

Don't attempt to get target properties for builtin instructions.

llvm-svn: 25672
 2006-01-27 01:44:09 +00:00
Duraid Madina
c4a1bfd13d almost got the HP-UX tester up.. :) 
llvm-svn: 25051
 2005-12-30 14:56:37 +00:00
Chris Lattner
a36ad00a9a Teach tblgen about instruction operands that have multiple MachineInstr 
operands, digging into them to find register values (used on X86).  Patch
by Evan Cheng!

llvm-svn: 24424
 2005-11-19 07:05:57 +00:00
Jim Laskey
4cb1e29b27 Allow itineraries to be passed through the Target Machine. 
llvm-svn: 24139
 2005-11-01 20:06:59 +00:00
Jeff Cohen
1a0261fe4f Keep VC++ happy. 
llvm-svn: 24137
 2005-11-01 18:04:06 +00:00
Jim Laskey
1c66d7fb02 Emit itinerary class in instruction info. 
llvm-svn: 24122
 2005-10-31 17:16:46 +00:00
Chris Lattner
d44a96088b Switch more code over to using getValueAsListOfDefs. Look at all the -'s. :) 
llvm-svn: 24074
 2005-10-28 22:59:53 +00:00
Chris Lattner
6c4ea26961 spell this variable right 
llvm-svn: 23095
 2005-08-26 20:42:52 +00:00
Chris Lattner
b474a0ab06 Expose a new flag to TargetInstrInfo 
llvm-svn: 23094
 2005-08-26 20:40:46 +00:00
Chris Lattner
17f0f9beae add a marker at the end of the instruction enum list 
llvm-svn: 23090
 2005-08-26 20:17:00 +00:00
Chris Lattner
9ceee53f9a Emit this: 
static const TargetOperandInfo OperandInfo6[] = { { &PPC32::CRRCRegClass }, { 0 }, };

instead of this:

static const TargetOperandInfo OperandInfo6[] = { { PPC32::CRRCRegisterClass }, { 0 }, };

For operand information, which does not require dynamic (startup-time)
initialization.

llvm-svn: 22931
 2005-08-19 20:29:14 +00:00
Chris Lattner
077a4e87c4 Emit real operand info for instructions. This currently works but is bad 
in one way: the generated tables require dynamic initialization for the
register classes.  This will be fixed in a future patch.

llvm-svn: 22919
 2005-08-19 18:46:26 +00:00
Chris Lattner
36f99a1374 For now, just emit empty operand info structures. 
llvm-svn: 22910
 2005-08-19 16:57:28 +00:00
Chris Lattner
7ab998463c now that all of the targets are clean w.r.t. the number of operands for each 
instruction defined, actually emit this to the InstrInfoDescriptor, which
allows an assert in the machineinstrbuilder to do some checking for us,
and is required by the dag->dag emitter

llvm-svn: 22895
 2005-08-19 00:59:49 +00:00
Chris Lattner
1f718aa8b5 revert this change, which causes breakage, temporarily 
llvm-svn: 22880
 2005-08-18 22:12:31 +00:00
Chris Lattner
b312f4d374 When emitting implicit use/def lists, only emit each unique list once. Though 
LLVM is able to merge identical static const globals, GCC isn't, and this caused
some bloat in the generated data.  This has a marginal effect on PPC, shrinking
the implicit sets from 10->4, but shrinks X86 from 179 to 23, a much bigger
reduction.

This should speed up the register allocator as well by reducing the dcache
footprint for this static data.

llvm-svn: 22879
 2005-08-18 21:36:47 +00:00
Chris Lattner
d3814ff064 Fill in the numOperands field of the TargetInstrDescriptor struct from the 
.td file.

llvm-svn: 22873
 2005-08-18 19:45:37 +00:00
Misha Brukman
960a8d47d7 Remove trailing whitespace 
llvm-svn: 21428
 2005-04-22 00:00:37 +00:00
Chris Lattner
f78580dcec Refactor code for numbering instructions into CodeGenTarget. 
llvm-svn: 19758
 2005-01-22 18:58:51 +00:00
Chris Lattner
2aef5783b0 Expose isConvertibleToThreeAddress and isCommutable bits to the code generator. 
llvm-svn: 19243
 2005-01-02 02:29:04 +00:00
Nate Begeman
bbf7945b61 Add support for the isLoad and isStore flags, needed by the instruction scheduler 
llvm-svn: 16554
 2004-09-28 21:01:45 +00:00
Chris Lattner
7a941d7691 Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG 
llvm-svn: 16553
 2004-09-28 18:38:01 +00:00
Chris Lattner
89ebd84bc2 Do not #include files into the llvm namespace 
llvm-svn: 15849
 2004-08-17 03:08:28 +00:00
Chris Lattner
ae25608f8b Instructions no longer need to have names. 
llvm-svn: 15399
 2004-08-01 08:38:17 +00:00
Chris Lattner
09d6e317a8 Add, and start using, the CodeGenInstruction class. This class represents 
an instance of the Instruction tablegen class.

llvm-svn: 15385
 2004-08-01 05:04:00 +00:00
Chris Lattner
07525455a6 Rename CodeGenWrappers.(cpp|h) -> CodeGenTarget.(cpp|h) 
llvm-svn: 15382
 2004-08-01 04:04:35 +00:00
Chris Lattner
2e8beb316b Finegrainify namespacification 
llvm-svn: 15381
 2004-08-01 03:55:39 +00:00
Chris Lattner
5c5c16ec21 Support new flag 
llvm-svn: 15355
 2004-07-31 02:07:26 +00:00
Brian Gaeke
d25f86d683 Put all LLVM code into the llvm namespace, as per bug 109. 
llvm-svn: 9903
 2003-11-11 22:41:34 +00:00
John Criswell
fc62e0f40d Added LLVM copyright header. 
llvm-svn: 9305
 2003-10-20 20:20:30 +00:00
Alkis Evlogimenos
74568bc9d4 Change MRegisterDesc::AliasSet, TargetInstrDescriptor::ImplicitDefs 
and TargetInstrDescriptor::ImplicitUses to always point to a null
terminated array and never be null. So there is no need to check for
pointer validity when iterating over those sets. Code that looked
like:

if (const unsigned* AS = TID.ImplicitDefs) {
  for (int i = 0; AS[i]; ++i) {
    // use AS[i]
  }
}

was changed to:

for (const unsigned* AS = TID.ImplicitDefs; *AS; ++AS) {
  // use *AS
}

llvm-svn: 8960
 2003-10-08 05:20:08 +00:00
Chris Lattner
1e1215d0d7 Move support/tools/* back into utils 
llvm-svn: 8875
 2003-10-05 19:27:59 +00:00