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Commit Graph

62003 Commits

Author SHA1 Message Date
Chris Lattner
e7c95bcd9e rip out even more sporadic v2f32 support.
llvm-svn: 107610
2010-07-05 04:38:33 +00:00
Chris Lattner
82c3b22a55 rip out the various v2f32 "mmx" handling logic, now that
v2f32 is illegal on x86.

llvm-svn: 107609
2010-07-05 04:36:27 +00:00
Chris Lattner
5c89561fc7 fix test on non-x86 hosts.
llvm-svn: 107608
2010-07-05 03:56:55 +00:00
Jakob Stoklund Olesen
9b1eb2b2ac Print symbolic subreg indices on REG_SEQUENCE and INSERT_SUBREG.
llvm-svn: 107602
2010-07-04 23:24:23 +00:00
Chris Lattner
cecaa1b061 Just rip v2f32 support completely out of the X86 backend. In
the example in the testcase, we now generate:

_test1:                                 ## @test1
	movss	4(%esp), %xmm0
	addss	8(%esp), %xmm0
	movl	12(%esp), %eax
	movss	%xmm0, (%eax)
	ret

instead of:

_test1:                                                     ## @test1
	subl	$20, %esp
	movl	24(%esp), %eax
	movq	%mm0, (%esp)
	movq	%mm0, 8(%esp)
	movss	(%esp), %xmm0
	addss	12(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$20, %esp
	ret

v2f32 support did not work reliably because most of the X86
backend didn't know it was legal.  It was apparently only added
to support returning source-level v2f32 values in MMX registers
in x86-32 mode.  If ABI compatibility is important on this
GCC-extended-vector type for some reason, then the frontend
should generate IR that returns v2i32 instead of v2f32.  However,
we generally don't try very hard to be abi compatible on gcc
extended vectors. 

llvm-svn: 107601
2010-07-04 23:07:25 +00:00
Chris Lattner
b17c4f3936 fix PR7518 - terrible codegen of <2 x float>, by only marking
v2f32 as legal in 32-bit mode.  It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.

llvm-svn: 107600
2010-07-04 22:57:10 +00:00
Chris Lattner
1e38d7d66d indentation
llvm-svn: 107599
2010-07-04 22:56:10 +00:00
Evan Cheng
9604b825a4 Infer alignments of fixed frame objects when they are constructed. This ensures remat'ed loads from fixed slots have the right alignments.
llvm-svn: 107591
2010-07-04 18:52:05 +00:00
Chris Lattner
58791300a3 indmemrem and lowerallocs are gone.
llvm-svn: 107587
2010-07-04 17:36:43 +00:00
Bill Wendling
689155c673 Revert r107583. I no longer think that this is the way to solve the problem.
llvm-svn: 107585
2010-07-04 09:16:57 +00:00
Bill Wendling
8a3ecba7a4 Mark sse_load_f32 and sse_load_f64 as having memory operands
(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.

llvm-svn: 107583
2010-07-04 08:59:55 +00:00
Gabor Greif
6fef76a35d back out r107580, I have seen what I wanted
llvm-svn: 107582
2010-07-04 08:59:25 +00:00
Bill Wendling
34feb1390d Proper indentation.
llvm-svn: 107581
2010-07-04 08:58:43 +00:00
Gabor Greif
e79dd85da8 [another test commit, just to tickle the selfhost buildbots; I'll back out in a few minutes]
second round of low-level interface squeeze-out:
making all of CallInst's low-level operand accessors
private

If you get compile errors I strongly urge you to
update your code.


I tried to write the necessary clues into the
header where the compiler may point to, but no
guarantees. It works for my GCC.

You have several options to update your code:

- you can use the v2.8 ArgOperand accessors
- you can go via a temporary CallSite
- you can upcast to, say, User and call its
  low-level accessors if your code is definitely
  operand-order agnostic.

If you run into serious problems, please
comment in below thread (and back out this
revision only if absolutely necessary):

<http://groups.google.com/group/llvm-dev/browse_thread/thread/64650cf343b28271>

llvm-svn: 107580
2010-07-04 07:42:31 +00:00
Eli Friedman
4cac2d90a2 Minor amendment to switch-lowering improvement.
llvm-svn: 107569
2010-07-03 08:43:32 +00:00
Eli Friedman
663bc3ce7e Note switch-lowering inefficiency.
llvm-svn: 107565
2010-07-03 07:38:12 +00:00
Bruno Cardoso Lopes
dc16024895 Add AVX SSE4.1 blend, mpsadbw and vdp
llvm-svn: 107560
2010-07-03 01:37:03 +00:00
Bruno Cardoso Lopes
9cbb625579 Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions
llvm-svn: 107558
2010-07-03 01:15:47 +00:00
Eric Christopher
ab076a2261 Fix typo.
llvm-svn: 107556
2010-07-03 01:09:18 +00:00
Bruno Cardoso Lopes
df02d037e4 Add AVX SSE4.1 Horizontal Minimum and Position instruction
llvm-svn: 107552
2010-07-03 00:49:21 +00:00
Evan Cheng
47f3a2db40 Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.
llvm-svn: 107550
2010-07-03 00:40:23 +00:00
Bruno Cardoso Lopes
e6b70efcb0 Add AVX SSE4.1 round instructions
llvm-svn: 107549
2010-07-03 00:37:44 +00:00
Jakob Stoklund Olesen
dba28ee3d8 Detect and handle COPY in many places.
This code is transitional, it will soon be possible to eliminate
isExtractSubreg, isInsertSubreg, and isMoveInstr in most places.

llvm-svn: 107547
2010-07-03 00:04:37 +00:00
Dan Gohman
de933eddb5 Document that BasicAA respects noalias, while InterproceduralBasicAA
does not.

llvm-svn: 107546
2010-07-02 23:52:36 +00:00
Dan Gohman
4848c9631b Describe which dependencies are relevant to noalias, and document how
AliasAnalyses have the choice to respect noalias.

llvm-svn: 107544
2010-07-02 23:46:54 +00:00
Bruno Cardoso Lopes
473863e456 Simple refactoring of SSE4.1 instructions, making room for the AVX forms
llvm-svn: 107540
2010-07-02 23:27:59 +00:00
Dan Gohman
7a6a35dbf7 Add some html anchors, to allow attributes to be linked to directly.
llvm-svn: 107538
2010-07-02 23:18:08 +00:00
Eric Christopher
2cf82a97f7 80-col fixup.
llvm-svn: 107537
2010-07-02 23:17:38 +00:00
Jakob Stoklund Olesen
8186b4c8d1 Add a new target independent COPY instruction and code to lower it.
The COPY instruction is intended to replace the target specific copy
instructions for virtual registers as well as the EXTRACT_SUBREG and
INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection
DAG.

COPY is lowered to native register copies by LowerSubregs.

llvm-svn: 107529
2010-07-02 22:29:50 +00:00
Bruno Cardoso Lopes
4931e183b5 - Add support for the rest of AVX SSE3 instructions
- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode

llvm-svn: 107523
2010-07-02 22:06:54 +00:00
Jakob Stoklund Olesen
4b0cb8209a Clean up TargetOpcodes.h a bit, and limit the number of places where the full
list of predefined instructions appear. Add some consistency checks.

Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it
is hardly worth the effort.

llvm-svn: 107520
2010-07-02 21:44:22 +00:00
Jim Grosbach
4f017c5fcb Custom inserters (e.g., conditional moves in Thumb1 can introduce
new basic blocks, and if used as a function argument, that can cause call frame
setup / destroy pairs to be split across a basic block boundary. That prevents
us from doing a simple assertion to check that the pairs match and alloc/
dealloc the same amount of space. Modify the assertion to only check the
amount allocated when there are matching pairs in the same basic block.

rdar://8022442

llvm-svn: 107517
2010-07-02 21:23:37 +00:00
Devang Patel
1c47157b66 MDString is already checked earlier.
llvm-svn: 107516
2010-07-02 21:13:23 +00:00
Evan Cheng
8c4e6ba789 Remove early IT block formation. It's not used.
llvm-svn: 107513
2010-07-02 21:07:09 +00:00
Evan Cheng
2954bb814e - Two-address pass should not assume unfolding is always successful.
- X86 unfolding should check if the instructions being unfolded has memoperands.
  If there is no memoperands, then it must assume conservative alignment. If this
  would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand
  etc. should not unfold the instruction.

llvm-svn: 107509
2010-07-02 20:36:18 +00:00
Dan Gohman
6a179b2376 Remove an unused enum.
llvm-svn: 107507
2010-07-02 20:20:50 +00:00
Dale Johannesen
df6db93a4d Propagate the AlignStack bit in InlineAsm's to the
PrologEpilog code, and use it to determine whether
the asm forces stack alignment or not.  gcc consistently
does not do this for GCC-style asms; Apple gcc inconsistently
sometimes does it for asm blocks.  There is no
convenient place to put a bit in either the SDNode or
the MachineInstr form, so I've added an extra operand
to each; unlovely, but it does allow for expansion for
more bits, should we need it.  PR 5125.  Some
existing testcases are affected.
The operand lists of the SDNode and MachineInstr forms
are indexed with awesome mnemonics, like "2"; I may
fix this someday, but not now.  I'm not making it any
worse.  If anyone is inspired I think you can find all
the right places from this patch.

llvm-svn: 107506
2010-07-02 20:16:09 +00:00
Jakob Stoklund Olesen
6d64b42774 Remove invalid assert
llvm-svn: 107505
2010-07-02 19:54:47 +00:00
Jakob Stoklund Olesen
ab1145ea8e Handle unindexed instructions in SlotIndices.
SlotIndexes::insertMachineInstrInMaps would crash when trying to insert an
instruction imediately after an unmapped debug value.

llvm-svn: 107504
2010-07-02 19:54:45 +00:00
Jakob Stoklund Olesen
d969cfd17f Properly handle debug values during inline spilling.
llvm-svn: 107503
2010-07-02 19:54:40 +00:00
Gabor Greif
7d4ffef197 beautify output
llvm-svn: 107500
2010-07-02 19:26:28 +00:00
Gabor Greif
92502bcde7 use ArgOperand API
llvm-svn: 107498
2010-07-02 19:08:46 +00:00
Dan Gohman
9d0f697ca8 Don't claim to preserve AliasAnalysis. First, this is doesn't actually
have any effect, and second, deleting stores can potentially invalidate
an AliasAnalysis, and there's currently no notification for this.

llvm-svn: 107496
2010-07-02 18:43:05 +00:00
Dan Gohman
04beeefa61 Reword the definition of the noalias attribute. The intention is for
the noalias argument on function attributes be usable to model the
C99 restrict keyword on arguments, and to allow AliasAnalysis to
consider a noalias-attributed argument to be an "identified object".

To support this, refactor a new "based on" concept out of the current
pointer aliasing "associated" concept. This "based on" concept is very
similar to (though it is not identical with) the "based on" concept
in C99.

Also, reword the definition of NoAlias to more closely describe the
concept that the optimizer uses.

llvm-svn: 107495
2010-07-02 18:41:32 +00:00
Jakob Stoklund Olesen
fc2900126b Rematerialize as much as possible before inserting spills and reloads.
This allows us to recognize the common case where all uses could be
rematerialized, and no stack slot allocation is necessary.

If some values could be fully rematerialized, remove them from the live range
before allocating a stack slot for the rest.

llvm-svn: 107492
2010-07-02 17:44:57 +00:00
Jim Grosbach
5836b352f1 80-column and trailing whitespace cleanup.
llvm-svn: 107490
2010-07-02 17:41:59 +00:00
Jim Grosbach
62c9cd6f1c grammar tweaks
llvm-svn: 107489
2010-07-02 17:38:34 +00:00
Bob Wilson
f96aab3079 Fix incorrect asm-printing of some NEON immediates. Fix weak testcase so
that it checks the immediate values, not just the instructions opcodes.
Radar 8110263.

llvm-svn: 107487
2010-07-02 17:23:44 +00:00
Gabor Greif
7c64164e6a use ArgOperand API (found by my previous commit)
llvm-svn: 107482
2010-07-02 13:37:16 +00:00
Gabor Greif
c3a036d6a2 back out r107480, it was just testing the waters anyway...
llvm-svn: 107481
2010-07-02 13:27:50 +00:00