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Commit Graph

81344 Commits

Author SHA1 Message Date
Richard Barton
201661d4bc Fixup VST1.32 with writeback instruction. Also re-factor non-writeback version.
llvm-svn: 153573
2012-03-28 10:18:11 +00:00
Chandler Carruth
e507ddfe74 Switch to WeakVHs in the value mapper, and aggressively prune dead basic
blocks in the function cloner. This removes the last case of trivially
dead code that I've been seeing in the wild getting inlined, analyzed,
re-inlined, optimized, only to be deleted. Nukes a FIXME from the
cleanup tests.

llvm-svn: 153572
2012-03-28 08:38:27 +00:00
Eric Christopher
0f1d5b363c More debug output.
llvm-svn: 153571
2012-03-28 07:34:36 +00:00
Eric Christopher
57ec9a8587 Fix the output of the DW_TAG_friend tag to include DW_AT_friend
and not the rest of the member tag.

Fixes PR11695

llvm-svn: 153570
2012-03-28 07:34:31 +00:00
Bill Wendling
853517869b Some whitespace cleanup.
llvm-svn: 153567
2012-03-28 04:17:34 +00:00
Bill Wendling
8d0a85a379 Use the correct filename for the error message.
llvm-svn: 153564
2012-03-28 02:39:06 +00:00
Bill Wendling
ec11c59c98 Use Nakamura's suggestion of bypassing using 'filename' and just the pointers directly.
llvm-svn: 153558
2012-03-28 01:30:51 +00:00
Akira Hatanaka
ef68ecdecc Turn off post-RA scheduler by default.
llvm-svn: 153557
2012-03-28 00:52:23 +00:00
Chad Rosier
23505e5bb6 Fix 80-column violation.
llvm-svn: 153556
2012-03-28 00:35:33 +00:00
Akira Hatanaka
3d463d748a Fix test case.
llvm-svn: 153555
2012-03-28 00:25:01 +00:00
Akira Hatanaka
d2ce66b138 Turn on post register allocation scheduler.
llvm-svn: 153554
2012-03-28 00:24:17 +00:00
Akira Hatanaka
fcd8108a1d Sort relocation entries before they are written out to a file. MIPS ABI
imposes a constraint that GOT16 referring to a local symbol or HI16 has to be
followed immediately by a matching LO16 relocation.

llvm-svn: 153553
2012-03-28 00:23:33 +00:00
Akira Hatanaka
a495c4cbaf Emit all directives except for ".cprestore" during asm printing rather than emit
them as machine instructions. Directives ".set noat" and ".set at" are now
emitted only at the beginning and end of a function except in the case where
they are emitted to enclose .cpload with an immediate operand that doesn't fit
in 16-bit field or unaligned load/stores.

Also, make the following changes:
- Remove function isUnalignedLoadStore and use a switch-case statement to
  determine whether an instruction is an unaligned load or store.

- Define helper function CreateMCInst which generates an instance of an MCInst
  from an opcode and a list of operands.

llvm-svn: 153552
2012-03-28 00:22:50 +00:00
Akira Hatanaka
8f8ee2351c Mark flag neverHasSideEffects of pattern-less instructions that do not have
any side effects.

llvm-svn: 153551
2012-03-28 00:21:37 +00:00
Francois Pichet
d04f23f329 MSVC doesn't like the mixing of declarations and statements in a .c file.
llvm-svn: 153549
2012-03-27 23:52:22 +00:00
Benjamin Kramer
4be5a4bca4 Add a note about a cute little fabs optimization.
llvm-svn: 153543
2012-03-27 22:42:42 +00:00
Benjamin Kramer
cc6159f7d9 Add two missed instcombines related to compares with nsw arithmetic.
llvm-svn: 153542
2012-03-27 22:03:19 +00:00
Bill Wendling
5c8d6c7990 Try to use the CWD if the path to the GCDA output is not available (e.g., the
executable has been moved to another machine). If that's not available
(read-only or something), then exit gracefully.
<rdar://problem/11111686>

llvm-svn: 153538
2012-03-27 21:17:04 +00:00
Akira Hatanaka
3853dcca58 Remove trailing white space.
llvm-svn: 153536
2012-03-27 20:35:51 +00:00
Lang Hames
6c935e3700 Use a SmallVector and linear lookup instead of a DenseSet - SourceMap values
will always be tiny sets, so DenseSet is overkill (SmallSet won't work as we
need iteration support). 

llvm-svn: 153529
2012-03-27 19:10:45 +00:00
Akira Hatanaka
0a613888c3 Add member EmitNOAT and its setter and getter functions to class MipsFunctionInfo.
If EmitNOAT is true, directives ".set noat" and ".set at" are emitted at the
beginning and end of a function. 

llvm-svn: 153528
2012-03-27 19:08:42 +00:00
Eric Christopher
324ff39943 Add a test for the previous commit. Also, remove two tests that were
testing a) the wrong behavior or b) something that I'm already testing
in the new test.

llvm-svn: 153525
2012-03-27 18:35:57 +00:00
Eric Christopher
5f34828440 Use DW_AT_low_pc for a single entry point into a routine.
Fixes PR10105

llvm-svn: 153524
2012-03-27 18:35:54 +00:00
Chad Rosier
d3fe1fcda9 Reapply r153423; the original commit was fine. The failing test, distray, had
undefined behavior, which Rafael was kind enough to fix.

Original commit message for r153423:
Use the new range metadata in computeMaskedBits and add a new optimization to
instruction simplify that lets us remove an and when loding a boolean value.

llvm-svn: 153521
2012-03-27 17:44:52 +00:00
Jakob Stoklund Olesen
48d7c2b088 ARMLoadStoreOptimizer invalidates register liveness.
This pass tries to update kill flags, but there are still many bugs.
Passes after the load/store optimizer don't need accurate liveness, so
don't even try.

<rdar://problem/11101911>

llvm-svn: 153519
2012-03-27 17:33:52 +00:00
Jakob Stoklund Olesen
21fd015586 Print SSA and liveness tracking flags in MF::print().
llvm-svn: 153518
2012-03-27 17:17:16 +00:00
Jakob Stoklund Olesen
01ae333053 Branch folding may invalidate liveness.
Branch folding can use a register scavenger to update liveness
information when required. Don't do that if liveness information is
already invalid.

llvm-svn: 153517
2012-03-27 17:06:09 +00:00
Jakob Stoklund Olesen
1f52931c1b Invalidate liveness in Thumb2ITBlockPass.
llvm-svn: 153516
2012-03-27 17:06:06 +00:00
Chris Lattner
bab5825de7 fix what looks like a real logic bug, found by PVS-Studio (part of PR12357)
llvm-svn: 153513
2012-03-27 16:27:21 +00:00
Jakob Stoklund Olesen
7ba0f121e5 Add an MRI::tracksLiveness() flag.
Late optimization passes like branch folding and tail duplication can
transform the machine code in a way that makes it expensive to keep the
register liveness information up to date. There is a fuzzy line between
register allocation and late scheduling where the liveness information
degrades.

The MRI::tracksLiveness() flag makes the line clear: While true,
liveness information is accurate, and can be used for register
scavenging. Once the flag is false, liveness information is not
accurate, and can only be used as a hint.

Late passes generally don't need the liveness information, but they will
sometimes use the register scavenger to help update it. The scavenger
enforces strict correctness, and we have to spend a lot of code to
update register liveness that may never be used.

llvm-svn: 153511
2012-03-27 15:13:58 +00:00
NAKAMURA Takumi
eb0805cb93 llvm/docs/*.html: Fix markups.
llvm-svn: 153508
2012-03-27 11:25:16 +00:00
Chandler Carruth
cd6d2689a0 Make a seemingly tiny change to the inliner and fix the generated code
size bloat. Unfortunately, I expect this to disable the majority of the
benefit from r152737. I'm hopeful at least that it will fix PR12345. To
explain this requires... quite a bit of backstory I'm afraid.

TL;DR: The change in r152737 actually did The Wrong Thing for
linkonce-odr functions. This change makes it do the right thing. The
benefits we saw were simple luck, not any actual strategy. Benchmark
numbers after a mini-blog-post so that I've written down my thoughts on
why all of this works and doesn't work...

To understand what's going on here, you have to understand how the
"bottom-up" inliner actually works. There are two fundamental modes to
the inliner:

1) Standard fixed-cost bottom-up inlining. This is the mode we usually
   think about. It walks from the bottom of the CFG up to the top,
   looking at callsites, taking information about the callsite and the
   called function and computing th expected cost of inlining into that
   callsite. If the cost is under a fixed threshold, it inlines. It's
   a touch more complicated than that due to all the bonuses, weights,
   etc. Inlining the last callsite to an internal function gets higher
   weighth, etc. But essentially, this is the mode of operation.

2) Deferred bottom-up inlining (a term I just made up). This is the
   interesting mode for this patch an r152737. Initially, this works
   just like mode #1, but once we have the cost of inlining into the
   callsite, we don't just compare it with a fixed threshold. First, we
   check something else. Let's give some names to the entities at this
   point, or we'll end up hopelessly confused. We're considering
   inlining a function 'A' into its callsite within a function 'B'. We
   want to check whether 'B' has any callers, and whether it might be
   inlined into those callers. If so, we also check whether inlining 'A'
   into 'B' would block any of the opportunities for inlining 'B' into
   its callers. We take the sum of the costs of inlining 'B' into its
   callers where that inlining would be blocked by inlining 'A' into
   'B', and if that cost is less than the cost of inlining 'A' into 'B',
   then we skip inlining 'A' into 'B'.

Now, in order for #2 to make sense, we have to have some confidence that
we will actually have the opportunity to inline 'B' into its callers
when cheaper, *and* that we'll be able to revisit the decision and
inline 'A' into 'B' if that ever becomes the correct tradeoff. This
often isn't true for external functions -- we can see very few of their
callers, and we won't be able to re-consider inlining 'A' into 'B' if
'B' is external when we finally see more callers of 'B'. There are two
cases where we believe this to be true for C/C++ code: functions local
to a translation unit, and functions with an inline definition in every
translation unit which uses them. These are represented as internal
linkage and linkonce-odr (resp.) in LLVM. I enabled this logic for
linkonce-odr in r152737.

Unfortunately, when I did that, I also introduced a subtle bug. There
was an implicit assumption that the last caller of the function within
the TU was the last caller of the function in the program. We want to
bonus the last caller of the function in the program by a huge amount
for inlining because inlining that callsite has very little cost.
Unfortunately, the last caller in the TU of a linkonce-odr function is
*not* the last caller in the program, and so we don't want to apply this
bonus. If we do, we can apply it to one callsite *per-TU*. Because of
the way deferred inlining works, when it sees this bonus applied to one
callsite in the TU for 'B', it decides that inlining 'B' is of the
*utmost* importance just so we can get that final bonus. It then
proceeds to essentially force deferred inlining regardless of the actual
cost tradeoff.

The result? PR12345: code bloat, code bloat, code bloat. Another result
is getting *damn* lucky on a few benchmarks, and the over-inlining
exposing critically important optimizations. I would very much like
a list of benchmarks that regress after this change goes in, with
bitcode before and after. This will help me greatly understand what
opportunities the current cost analysis is missing.

Initial benchmark numbers look very good. WebKit files that exhibited
the worst of PR12345 went from growing to shrinking compared to Clang
with r152737 reverted.

- Bootstrapped Clang is 3% smaller with this change.
- Bootstrapped Clang -O0 over a single-source-file of lib/Lex is 4%
  faster with this change.

Please let me know about any other performance impact you see. Thanks to
Nico for reporting and urging me to actually fix, Richard Smith, Duncan
Sands, Manuel Klimek, and Benjamin Kramer for talking through the issues
today.

llvm-svn: 153506
2012-03-27 10:48:28 +00:00
Craig Topper
bf6a47d0ec Prune some includes
llvm-svn: 153502
2012-03-27 07:54:11 +00:00
Craig Topper
6bb276ae72 Remove unnecessary llvm:: qualifications
llvm-svn: 153500
2012-03-27 07:21:54 +00:00
Akira Hatanaka
e41c1a7f91 Pass the llvm IR pointer value and offset to the constructor of
MachinePointerInfo when getStore is called to create a node that stores an
argument passed in register to the stack. Without this change, the post RA 
scheduler will fail to discover the dependencies between the stores
instructions and the instructions that load from a structure passed by value. 

The link to the related discussion is here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-March/048055.html

llvm-svn: 153499
2012-03-27 03:13:56 +00:00
Akira Hatanaka
55149b37e0 Fix bug in LowerConstantPool.
llvm-svn: 153498
2012-03-27 02:55:31 +00:00
Akira Hatanaka
1ae82e61f1 Add T9 to the list of live-in registers of the entry basic block.
llvm-svn: 153497
2012-03-27 02:46:25 +00:00
Akira Hatanaka
ccaa02d6ed Retrieve and add the offset of a symbol in applyFixup rather than retrieve and
set it in MipsMCCodeEmitter::getMachineOpValue. Assert in getMachineOpValue if
MachineOperand MO is of an unexpected type. 

llvm-svn: 153494
2012-03-27 02:33:05 +00:00
Akira Hatanaka
b286eb94cf Define function MipsGetSymAndOffset which returns a fixup's symbol and the
offset applied to it.

llvm-svn: 153493
2012-03-27 02:04:18 +00:00
Evan Cheng
2ea4c182ae Post-ra LICM should take care not to hoist an instruction that would clobber a
register that's read by the preheader terminator.

rdar://11095580

llvm-svn: 153492
2012-03-27 01:50:58 +00:00
Akira Hatanaka
88d8bcdbea Rewrite computation of Value in adjustFixupValue so that the upper 48-bits are
cleared. No functionality change.

llvm-svn: 153491
2012-03-27 01:50:08 +00:00
Lang Hames
6e80e967f5 During MachineCopyPropagation a register may be the source operand of multiple
copies being considered for removal. Make sure to track all of the copies,
rather than just the most recent encountered, by holding a DenseSet instead of
an unsigned in SrcMap.

No test case - couldn't reduce something with a sane size.

llvm-svn: 153487
2012-03-27 00:44:47 +00:00
Akira Hatanaka
57250eff2a Reserve hardware registers.
llvm-svn: 153486
2012-03-27 00:40:56 +00:00
Evan Cheng
72cf12e416 ARM has a peephole optimization which looks for a def / use pair. The def
produces a 32-bit immediate which is consumed by the use. It tries to 
fold the immediate by breaking it into two parts and fold them into the
immmediate fields of two uses. e.g
       movw    r2, #40885
       movt    r3, #46540
       add     r0, r0, r3
=>
       add.w   r0, r0, #3019898880
       add.w   r0, r0, #30146560
;
However, this transformation is incorrect if the user produces a flag. e.g.
       movw    r2, #40885
       movt    r3, #46540
       adds    r0, r0, r3
=>
       add.w   r0, r0, #3019898880
       adds.w  r0, r0, #30146560
Note the adds.w may not set the carry flag even if the original sequence
would.

rdar://11116189

llvm-svn: 153484
2012-03-26 23:31:00 +00:00
Lang Hames
bc5e9b1c25 Add a debug option to dump PBQP graphs during register allocation.
llvm-svn: 153483
2012-03-26 23:07:23 +00:00
Andrew Trick
88a52fd943 SCEV fix: Handle loop invariant loads.
Fixes PR11882: NULL dereference in ComputeLoadConstantCompareExitLimit.

llvm-svn: 153480
2012-03-26 22:33:59 +00:00
Bill Wendling
23830b53f3 Add 'undef's to make SWIG happier. Patch by Baozeng Ding.
llvm-svn: 153479
2012-03-26 22:15:12 +00:00
Eric Christopher
1ba37ca43c Add InitializeNativeTargetDisassembler function.
Patch by Ojab.

llvm-svn: 153476
2012-03-26 21:56:56 +00:00
Andrew Trick
e13ce38b53 Unit test for PR11950: LSR crash.
llvm-svn: 153472
2012-03-26 21:45:37 +00:00
Eric Christopher
c1784e9de8 Use the file in the inlined die rather than the compile unit for
backtrace locations.

Testcase forthcoming, but I wanted to get some testing here.

Should fix:

PR12323
PR12314
rdar://11091100

llvm-svn: 153471
2012-03-26 21:38:38 +00:00