4 Commits

Author	SHA1	Message	Date
Owen Anderson	af51fd9868	invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. ... llvm-svn: 138653	2011-08-26 20:43:14 +00:00
Owen Anderson	decc5fcced	Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. ... llvm-svn: 137323	2011-08-11 18:55:42 +00:00
Owen Anderson	ffe1c55752	Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. ... This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144	2011-08-09 20:55:18 +00:00
Johnny Chen	b07cb8fee1	Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as ... invalid instructions. llvm-svn: 129286	2011-04-11 18:34:12 +00:00