James Molloy
ac057f13a5
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
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llvm-svn: 139250
2011-09-07 19:42:28 +00:00
Owen Anderson
ffe1c55752
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
llvm-svn: 137144
2011-08-09 20:55:18 +00:00
Owen Anderson
7a380bac06
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
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llvm-svn: 135290
2011-07-15 18:46:47 +00:00
Johnny Chen
197d67a987
The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions
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(single element or n-element structure to all lanes).
llvm-svn: 129550
2011-04-15 00:10:45 +00:00
Johnny Chen
0b8e3b20f7
Add a VEXT test.
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llvm-svn: 129111
2011-04-07 22:04:01 +00:00
Johnny Chen
1f028bb23e
The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values
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for USAD8 and USADA8.
rdar://problem/9247060
llvm-svn: 129047
2011-04-07 01:05:52 +00:00
Johnny Chen
96fd9620c8
A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"
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Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.
rdar://problem/9239922
rdar://problem/9239596
llvm-svn: 129027
2011-04-06 20:49:02 +00:00
Johnny Chen
b3130a03a7
Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.
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Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.
rdar://problem/9240648
llvm-svn: 129015
2011-04-06 18:27:46 +00:00
Johnny Chen
359b9a2331
A7.3 register encoding
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Qd -> bit[12] == 0
Qn -> bit[16] == 0
Qm -> bit[0] == 0
If one of these bits is 1, the instruction is UNDEFINED.
rdar://problem/9238399
rdar://problem/9238445
llvm-svn: 128949
2011-04-05 22:57:07 +00:00
Johnny Chen
7fb247299a
Fix incorrect alignment for NEON VST2b32_UPD.
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rdar://problem/9225433
llvm-svn: 128841
2011-04-04 20:35:31 +00:00
Johnny Chen
9672fe0126
Handle the added VBICiv*i* NEON instructions, too.
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llvm-svn: 128243
2011-03-24 22:04:39 +00:00
Johnny Chen
f6655e82b3
The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the
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VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case.
llvm-svn: 128226
2011-03-24 18:40:38 +00:00
Johnny Chen
a31ae5ca74
Add one more test case for VFP Load/Store Multiple (vpop).
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llvm-svn: 128106
2011-03-22 20:21:08 +00:00
Dale Johannesen
05a7c613fa
Segregate tests by target.
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llvm-svn: 119050
2010-11-14 18:14:32 +00:00
