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Commit Graph

1661 Commits

Author SHA1 Message Date
Dan Gohman
cfdb39da9c Remove the implicit conversion from SDOperandPtr to SDOperand*; this
may fix a build error on Visual Studio.

llvm-svn: 49876
2008-04-17 23:02:12 +00:00
Roman Levenstein
2a2a386127 Minor clean-up based on Dan's comments.
llvm-svn: 49844
2008-04-17 09:29:48 +00:00
Nicolas Geoffray
1f3211af01 Correlate stubs with functions in JIT: when emitting a stub, the JIT tells the memory manager which function
the stub will resolve.

llvm-svn: 49814
2008-04-16 20:46:05 +00:00
Roman Levenstein
728d59166f Ongoing work on improving the instruction selection infrastructure:
Rename SDOperandImpl back to SDOperand.
Introduce the SDUse class that represents a use of the SDNode referred by
an SDOperand. Now it is more similar to Use/Value classes.

Patch is approved by Dan Gohman.

llvm-svn: 49795
2008-04-16 16:15:27 +00:00
Evan Cheng
6d05ce493b Rewrite LiveVariable liveness computation. The new implementation is much simplified. It eliminated the nasty recursive routines and removed the partial def / use bookkeeping. There is also potential for performance improvement by replacing the conservative handling of partial physical register definitions. The code is currently disabled until live interval analysis is taught of the name scheme.
This patch also fixed a couple of nasty corner cases.

llvm-svn: 49784
2008-04-16 09:46:40 +00:00
Dale Johannesen
f45cadf9d2 Make 64-to-32 bit truncations explicit (prevent warnings).
All values here fit in 32 bits.

llvm-svn: 49736
2008-04-15 18:44:59 +00:00
Nicolas Geoffray
7e0110f724 Change Divided flag to Split, as suggested by Evan
llvm-svn: 49715
2008-04-15 08:08:50 +00:00
Dan Gohman
3b99b3c807 Treat EntryToken nodes as "passive" so that they aren't added to the
ScheduleDAG; they don't correspond to any actual instructions so they
don't need to be scheduled.

This fixes a bug where the EntryToken was being scheduled multiple
times in some cases, though it ended up not causing any trouble because 
EntryToken doesn't expand into anything. With this fixed the schedulers
reliably schedule the expected number of units, so we can check this
with an assertion.

This requires a tweak to test/CodeGen/X86/loop-hoist.ll because it
ends up getting scheduled differently in a trivial way, though it was
enough to fool the prcontext+grep that the test does.

llvm-svn: 49701
2008-04-15 01:22:18 +00:00
Dan Gohman
dfa422fe9e In -view-sunit-dags, display "special" chain dependencies as cyan
instead of blue to distinguish them from regular dependencies.

llvm-svn: 49696
2008-04-14 23:15:07 +00:00
Dan Gohman
8d46278998 Fix const-correctness issues with the SrcValue handling in the
memory intrinsic expansion code.

llvm-svn: 49666
2008-04-14 17:55:48 +00:00
Nicolas Geoffray
ad5556e8ba Add a divided flag for the first piece of an argument divided into mulitple parts. Fixes PR1643
llvm-svn: 49611
2008-04-13 13:40:22 +00:00
Dan Gohman
15edbf989f Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.

Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.

This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.

Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.

This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.

llvm-svn: 49572
2008-04-12 04:36:06 +00:00
Evan Cheng
b389b78462 Use of implicit_def is not part of live interval. Create empty intervals for the uses when the live interval is being spilled.
llvm-svn: 49542
2008-04-11 17:53:36 +00:00
Evan Cheng
52208a738f Allow registers defined by implicit_def to be clobbered.
llvm-svn: 49512
2008-04-10 23:47:53 +00:00
Dan Gohman
aa52f1c5b0 Fix a typo in a comment.
llvm-svn: 49502
2008-04-10 22:27:06 +00:00
Dan Gohman
f03c4d87c0 Update comments to use 2.0 syntax type names.
llvm-svn: 49442
2008-04-09 18:24:25 +00:00
Dan Gohman
d7301ea935 Rename MemOperand to MachineMemOperand. This was suggested by
review feedback from Chris quite a while ago. No functionality
change.

llvm-svn: 49348
2008-04-07 19:35:22 +00:00
Roman Levenstein
b40d332929 Re-commit of the r48822, where the infinite looping problem discovered
by Dan Gohman is fixed.

llvm-svn: 49330
2008-04-07 10:06:32 +00:00
Evan Cheng
9045e3dd2f Forgot this.
llvm-svn: 49247
2008-04-05 02:17:58 +00:00
Evan Cheng
ff9c1655de Special handling of zero-sized live intervals.
llvm-svn: 49167
2008-04-03 16:40:27 +00:00
Evan Cheng
6250bfbd3e - Treat a live range defined by an implicit_def as a zero-sized one.
- Eliminate an implicit_def when it's being spilled.

llvm-svn: 49166
2008-04-03 16:39:43 +00:00
Evan Cheng
53c8db51dd Start of a series of patches related to implicit_def.
There is no point in creating a long live range defined by an implicit_def. Scheduler now duplicates implicit_def instruction for each of its uses. Therefore, if an implicit_def node has multiple uses, it will become a number of very short live ranges, rather than a long one. This will make coalescer's job easier.

llvm-svn: 49164
2008-04-03 16:36:07 +00:00
Evan Cheng
497c607fae Backing out 48222 temporarily.
llvm-svn: 49124
2008-04-03 03:13:16 +00:00
Evan Cheng
748a0c9215 Now that I am told MachineRegisterInfo also tracks physical register uses / defs, I can do away with the horribleness I introduced a while back. It's impossible to detect if there is any use of a physical register below an instruction (and before any def of the register) with some cheap book keeping.
llvm-svn: 49105
2008-04-02 18:04:08 +00:00
Evan Cheng
4e841d67ed Remove #include<map> from LiveVariables.h. Not referenced.
llvm-svn: 49099
2008-04-02 17:23:50 +00:00
Anton Korobeynikov
d3330dfbf6 Add new CC lowering rule: provide a list of registers, which can be 'shadowed',
when some another register is used for argument passing.
Currently is used on Win64.

llvm-svn: 49079
2008-04-02 05:23:57 +00:00
Dale Johannesen
79633a914f Recommitting EH patch; this should answer most of the
review feedback.
-enable-eh is still accepted but doesn't do anything.
EH intrinsics use Dwarf EH if the target supports that,
and are handled by LowerInvoke otherwise.
The separation of the EH table and frame move data is,
I think, logically figured out, but either one still
causes full EH info to be generated (not sure how to
split the metadata correctly).
MachineModuleInfo::needsFrameInfo is no longer used and
is removed.

llvm-svn: 49064
2008-04-02 00:25:04 +00:00
Chris Lattner
c7cc29f2a9 update comment.
llvm-svn: 49010
2008-04-01 00:54:39 +00:00
Evan Cheng
4d86275d23 Cosmetic change.
llvm-svn: 48935
2008-03-29 01:04:05 +00:00
Duncan Sands
80f14df923 Rename getAnyLoad to getLoad is suggested by Evan.
llvm-svn: 48914
2008-03-28 09:45:24 +00:00
Duncan Sands
3d613421f1 Implement LegalizeTypes support for softfloat LOAD.
In order to handle indexed nodes I had to introduce
a new constructor, and since I was there I factorized
the code in the various load constructors.

llvm-svn: 48894
2008-03-27 20:23:40 +00:00
Dan Gohman
199ab29337 Avoid creating chain dependencies from CopyToReg nodes to load and store
nodes. This doesn't currently have much impact the generated code, but it
does produce simpler-looking SelectionDAGs, and consequently
simpler-looking ScheduleDAGs, because there are fewer spurious
dependencies.

In particular, CopyValueToVirtualRegister now uses the entry node as the
input chain dependency for new CopyToReg nodes instead of calling getRoot
and depending on the most recent memory reference.

Also, rename UnorderedChains to PendingExports and pull it up from being
a local variable in SelectionDAGISel::BuildSelectionDAG to being a
member variable of SelectionDAGISel, so that it doesn't have to be
passed around to all the places that need it.

llvm-svn: 48893
2008-03-27 19:56:19 +00:00
Roman Levenstein
55b8822511 Use a linked data structure for the uses lists of an SDNode, just like
LLVM Value/Use does and MachineRegisterInfo/MachineOperand does.
This allows constant time for all uses list maintenance operations.

The idea was suggested by Chris. Reviewed by Evan and Dan.
Patch is tested and approved by Dan.

On normal use-cases compilation speed is not affected. On very big basic
blocks there are compilation speedups in the range of 15-20% or even better. 

llvm-svn: 48822
2008-03-26 12:39:26 +00:00
Dan Gohman
22002efa15 A quick nm audit turned up several fixed tables and objects that were
marked read-write. Use const so that they can be allocated in a
read-only segment.

llvm-svn: 48800
2008-03-25 21:45:14 +00:00
Evan Cheng
874aee2eec Teach DAG combiner to commute commutable binary nodes in order to achieve sdisel CSE.
llvm-svn: 48673
2008-03-22 01:55:50 +00:00
Dan Gohman
a363ba510c Don't include <map> in Pass.h, which doesn't need it. This requires
adding <map> to many files that actually do need it.

llvm-svn: 48667
2008-03-21 23:51:57 +00:00
Duncan Sands
4153fc30c9 Introduce a new node for holding call argument
flags.  This is needed by the new legalize types
infrastructure which wants to expand the 64 bit
constants previously used to hold the flags on
32 bit machines.  There are two functional changes:
(1) in LowerArguments, if a parameter has the zext
attribute set then that is marked in the flags;
before it was being ignored; (2) PPC had some bogus
code for handling two word arguments when using the
ELF 32 ABI, which was hard to convert because of
the bogusness.  As suggested by the original author
(Nicolas Geoffray), I've disabled it for the moment.
Tested with "make check" and the Ada ACATS testsuite.

llvm-svn: 48640
2008-03-21 09:14:45 +00:00
Evan Cheng
3d9309c11d Fix live variables issues:
1. If part of a register is re-defined, an implicit kill and an implicit def are added to denote read / mod / write. However, this should only be necessary if the register is actually read later. This is a performance issue.
2. If a sub-register is being defined, and it doesn't have a previous use, do not add a implicit kill to the last use of a super-register:
   = EAX, AX<imp-use,kill>
...
AX =
In this case, EAX is live but AX is killed, this is wrong and will cause the coalescer to do bad things.

llvm-svn: 48521
2008-03-19 00:52:20 +00:00
Evan Cheng
11d2c09adc Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
llvm-svn: 48380
2008-03-15 00:03:38 +00:00
Evan Cheng
b49600c090 Back out r48353. Not needed.
llvm-svn: 48375
2008-03-14 22:01:01 +00:00
Evan Cheng
98eaed9fbc Add an MO_Undef MachineOperandType, intended for INSERT_SUBREG. Next up MO_Undead.
llvm-svn: 48353
2008-03-14 01:47:49 +00:00
Evan Cheng
d466e7a521 Forgot this.
llvm-svn: 48349
2008-03-14 00:17:29 +00:00
Dan Gohman
89e8681ac5 Fix a typo in a comment.
llvm-svn: 48345
2008-03-13 23:04:27 +00:00
Evan Cheng
a3b56a661c Improve VarInfo::removeKill() by using std::find instead of linear search.
llvm-svn: 48321
2008-03-13 02:42:55 +00:00
Evan Cheng
b9fc5d6d07 Refactor some code out of MachineSink into a MachineInstr query.
llvm-svn: 48311
2008-03-13 00:44:09 +00:00
Evan Cheng
620fd19798 Experimental scheduler change to schedule / coalesce the copies added for function livein's. Take 2008-03-10-RegAllocInfLoop.ll, the schedule looks like this after these copies are inserted:
entry: 0x12049d0, LLVM BB @0x1201fd0, ID#0:
Live Ins: %EAX %EDX %ECX
        %reg1031<def> = MOVPC32r 0
        %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
        %reg1028<def> = MOV32rr %EAX
        %reg1029<def> = MOV32rr %EDX
        %reg1030<def> = MOV32rr %ECX
        %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x1201910 + 0]
        %reg1025<def> = MOV32rr %reg1029
        %reg1026<def> = MOV32rr %reg1030
        %reg1024<def> = MOV32rr %reg1028

The copies unnecessarily increase register pressure and it will end up requiring a physical register to be spilled.

With -schedule-livein-copies:
entry: 0x12049d0, LLVM BB @0x1201fa0, ID#0:
Live Ins: %EAX %EDX %ECX
        %reg1031<def> = MOVPC32r 0
        %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
        %reg1024<def> = MOV32rr %EAX
        %reg1025<def> = MOV32rr %EDX
        %reg1026<def> = MOV32rr %ECX
        %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x12018e0 + 0]

Much better!

llvm-svn: 48307
2008-03-12 22:19:41 +00:00
Duncan Sands
05eb212b2d Don't try to extract an i32 from an f64. This
getCopyToParts problem was noticed by the new
LegalizeTypes infrastructure.  In order to avoid
this kind of thing in the future I've added a
check that EXTRACT_ELEMENT is only used with
integers.  Once LegalizeTypes is up and running
most likely BUILD_PAIR and EXTRACT_ELEMENT can
be removed, in favour of using apints instead.

llvm-svn: 48294
2008-03-12 20:30:08 +00:00
Evan Cheng
59831b0358 Document an implementation detail about EXTRACT_SUBREG and INSERT_SUBREG sub-register operand.
llvm-svn: 48283
2008-03-12 07:52:15 +00:00
Dan Gohman
8e3c88c4e9 Use PassManagerBase instead of FunctionPassManager for functions
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.

llvm-svn: 48256
2008-03-11 22:29:46 +00:00
Evan Cheng
af1c76846d When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting.
llvm-svn: 48218
2008-03-11 07:19:34 +00:00