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Commit Graph

92330 Commits

Author SHA1 Message Date
Elena Demikhovsky
9523e885e5 Removed SSEPacked domain from all forms (AVX, SSE, signed, unsigned) scalar compare instructions, like COMISS, COMISD.
No functional changes.

llvm-svn: 182371
2013-05-21 12:04:22 +00:00
Ulrich Weigand
ec9f537092 Alternative fix for problem addressed in r182233
Revision r182233 partially reverted the change in r181200 to simplify
JIT unif test #ifdefs, because that change caused a link error on some
host operating systems where the export list requires the following
symbols to be defined:

 JITTest_AvailableExternallyFunction
 JITTest_AvailableExternallyGlobal

As discussed on the list, the commit reverts r182233 (and re-installs
the full r181200 change), and instead fixes the link problem by moving
those two symbols to the top of the file and unconditionally defining
them.

llvm-svn: 182367
2013-05-21 10:30:59 +00:00
Benjamin Kramer
6b339bee4e X86: When emulating unsigned PCMPGTQ with PCMPGTD, fix the sign bit for the smaller type.
Otherwise we'll get a mix of signed and unsigned compares.
Fixes PR15977.

llvm-svn: 182364
2013-05-21 09:58:54 +00:00
Richard Sandiford
10059d8172 [SystemZ] Tighten branch tests
After r182274, the branches in these tests must always be short.

llvm-svn: 182358
2013-05-21 08:53:17 +00:00
Benjamin Kramer
5872fe13c9 DAGCombine: Avoid an edge case where it tried to create an i0 type for (x & 0) == 0.
Fixes PR16083.

llvm-svn: 182357
2013-05-21 08:51:09 +00:00
Richard Sandiford
bb9bbbf6cc Fix indentation
llvm-svn: 182356
2013-05-21 08:48:24 +00:00
Eric Christopher
c1ebc34238 Add cmake bits for md5.
llvm-svn: 182349
2013-05-21 01:30:38 +00:00
Eric Christopher
9b050277c3 Add an md5 library derived from a public domain implementation for dwarf4
type signature computation.

llvm-svn: 182348
2013-05-21 01:28:35 +00:00
Reed Kotler
81c5979b12 Add checks that the proper predeined stubs are being called to the test case.
These were accidentally omitted.

llvm-svn: 182347
2013-05-21 01:27:36 +00:00
Manman Ren
d272ba0f1a Dwarf: use a single line table to generate assembly when .loc is used.
This is to fix PR15408 where an undefined symbol Lline_table_start1 is used.
Since we do not generate the debug_line section when .loc is used,
Lline_table_start1 is not emitted and we can't refer to it when calculating
at_stmt_list for a compile unit.

llvm-svn: 182344
2013-05-21 00:57:22 +00:00
Reed Kotler
2d5f41cb35 Add some additional functions to the list of helper functions for
pic calls. These need to be there so we don't try and use helper
functions when we call those.

As part of this, make sure that we properly exclude helper functions in pic
mode when indirect calls are involved.

llvm-svn: 182343
2013-05-21 00:50:30 +00:00
Richard Smith
6a4438b7ff Comment update: these things are called "configuration names" these days, not
"triples". Also remove the implication that they're only used for specifying a
target.

llvm-svn: 182335
2013-05-20 23:55:41 +00:00
Sean Silva
f92aea7789 LangRef.rst: Clarify how basic blocks without named label are handled.
Describe that they are assigned numbered label using the same counter
as for unnamed temporaries.

Based on http://llvm.org/bugs/show_bug.cgi?id=16043 and mailing list
discussion.

Patch by Paul Sokolovsky!

llvm-svn: 182332
2013-05-20 23:31:12 +00:00
David Blaikie
107b1a9b43 PR14606: Debug Info for namespace aliases/DW_TAG_imported_module
This resolves the last of the PR14606 failures in the GDB 7.5 test
suite by implementing an optional name field for
DW_TAG_imported_modules/DIImportedEntities and using that to implement
C++ namespace aliases (eg: "namespace X = Y;").

llvm-svn: 182328
2013-05-20 22:50:35 +00:00
Daniel Dunbar
8a10ff14a8 [docs] Minor doc tweaks.
llvm-svn: 182324
2013-05-20 22:39:48 +00:00
Bill Wendling
3688f3fab9 The DWARF EH pass doesn't need the TargetMachine, only the TargetLoweringBase like the other EH passes.
llvm-svn: 182321
2013-05-20 21:54:18 +00:00
Bill Wendling
c46fd61418 No need to store the TargetMachine variable in this class.
llvm-svn: 182317
2013-05-20 21:28:28 +00:00
Bill Wendling
6ab76e414f Remove unused #include.
llvm-svn: 182315
2013-05-20 20:59:12 +00:00
Hal Finkel
cf203aeadb Rename LoopSimplify.h to LoopUtils.h
As discussed, LoopUtils.h is a better name.

llvm-svn: 182314
2013-05-20 20:46:30 +00:00
Sebastian Pop
7ccb90a1cc add polly to check-all
llvm-svn: 182308
2013-05-20 18:49:15 +00:00
Akira Hatanaka
05711091c4 [mips] Add (setne $lhs, 0) instruction selection pattern.
llvm-svn: 182307
2013-05-20 18:18:07 +00:00
Akira Hatanaka
96de87d87c [mips] Trap on integer division by zero.
By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.

llvm-svn: 182306
2013-05-20 18:07:43 +00:00
Hal Finkel
077bcf0963 Remove copied preheader insertion logic from PPCCTRLoops
Now that the preheader insertion logic in LoopSimplify is externally exposed,
use it, and remove the copy-and-pasted version.

No functionality change intended.

llvm-svn: 182300
2013-05-20 16:47:10 +00:00
Hal Finkel
4692993a01 Expose InsertPreheaderForLoop from LoopSimplify to other passes
Other passes, PPC counter-loop formation for example, also need to add loop
preheaders outside of the regular loop simplification pass. This makes
InsertPreheaderForLoop a global function so that it can be used by other
passes.

No functionality change intended.

llvm-svn: 182299
2013-05-20 16:47:07 +00:00
Justin Holewinski
2d2a08ee5e [NVPTX] Fix mis-use of CurrentFnSym in NVPTXAsmPrinter. This was causing a symbol name error in the output PTX.
llvm-svn: 182298
2013-05-20 16:42:18 +00:00
Justin Holewinski
3c0938687d [NVPTX] Add programmatic interface to NVVMReflect pass
llvm-svn: 182297
2013-05-20 16:42:16 +00:00
Hal Finkel
b008faddc8 Rename PPC MTCTRse to MTCTRloop
As the pairing of this instruction form with the bdnz/bdz branches is now
enforced by the verification pass, make it clear from the name that these
are used only for counter-based loops.

No functionality change intended.

llvm-svn: 182296
2013-05-20 16:08:37 +00:00
Hal Finkel
e230e28ec5 Add a PPCCTRLoops verification pass
When asserts are enabled, this adds a verification pass for PPC counter-loop
formation. Unfortunately, without sacrificing code quality, there is no better
way of forming counter-based loops except at the (late) IR level. This means
that we need to recognize, at the IR level, anything which might turn into a
function call (or indirect branch). Because this is currently a finite set of
things, and because SelectionDAG lowering is basic-block local, this can be
done. Nevertheless, it is fragile, and failure results in a miscompile. This
verification pass checks that all (reachable) counter-based branches are
dominated by a loop mtctr instruction, and that no instructions in between
clobber the counter register. If these conditions are not satisfied, then an
ICE will be triggered.

In short, this is to help us sleep better at night.

llvm-svn: 182295
2013-05-20 16:08:17 +00:00
Benjamin Kramer
66d4343951 R600: Fix bug detected by GCC warning.
R600TextureIntrinsicsReplacer.cpp:232: warning: the address of ‘ArgsType’ will always evaluate as ‘true’

This doesn't have any effect on the output as a vararg intrinsic behaves the
same way as a non-vararg one.

llvm-svn: 182293
2013-05-20 15:58:43 +00:00
Tom Stellard
6cdacd1792 R600: Fix rotr.ll on non-asserts builds
The -debug-only option is only available on asserts builds.

llvm-svn: 182291
2013-05-20 15:28:48 +00:00
Tom Stellard
8c433f74be R600/SI: Use a multiclass for MUBUF_Load_Helper
This will simplify the instructions and also the pattern definitions.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182288
2013-05-20 15:02:31 +00:00
Tom Stellard
20519ba9b1 R600/SI: Add a pattern for S_LOAD_DWORDX2_* instructions
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182287
2013-05-20 15:02:28 +00:00
Tom Stellard
d72698331e R600/SI: Add pattern for rotr
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182286
2013-05-20 15:02:24 +00:00
Tom Stellard
5ca265d214 R600: Swap the legality of rotl and rotr
The hardware supports rotr and not rotl.

llvm-svn: 182285
2013-05-20 15:02:19 +00:00
Tom Stellard
1609774b15 R600/SI: Add patterns for 64-bit shift operations
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182284
2013-05-20 15:02:12 +00:00
Tom Stellard
ad64547aac R600/SI: Use the same names for VOP3 operands and encoding fields
This makes it possible to reorder the operands without breaking the
encoding.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182283
2013-05-20 15:02:08 +00:00
Tom Stellard
9e5dc799d9 R600/SI: Make fitsRegClass() operands const
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182282
2013-05-20 15:02:01 +00:00
Mihai Popa
d42b1e0685 VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review).
llvm-svn: 182281
2013-05-20 14:57:05 +00:00
Mihai Popa
dbf8d46d3c Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL).
llvm-svn: 182279
2013-05-20 14:42:43 +00:00
Richard Sandiford
cc815ef1d8 [SystemZ] Add long branch pass
Before this change, the SystemZ backend would use BRCL for all branches
and only consider shortening them to BRC when generating an object file.
E.g. a branch on equal would use the JGE alias of BRCL in assembly output,
but might be shortened to the JE alias of BRC in ELF output.  This was
a useful first step, but it had two problems:

(1) The z assembler isn't traditionally supposed to perform branch shortening
    or branch relaxation.  We followed this rule by not relaxing branches
    in assembler input, but that meant that generating assembly code and
    then assembling it would not produce the same result as going directly
    to object code; the former would give long branches everywhere, whereas
    the latter would use short branches where possible.

(2) Other useful branches, like COMPARE AND BRANCH, do not have long forms.
    We would need to do something else before supporting them.

    (Although COMPARE AND BRANCH does not change the condition codes,
    the plan is to model COMPARE AND BRANCH as a CC-clobbering instruction
    during codegen, so that we can safely lower it to a separate compare
    and long branch where necessary.  This is not a valid transformation
    for the assembler proper to make.)

This patch therefore moves branch relaxation to a pre-emit pass.
For now, calls are still shortened from BRASL to BRAS by the assembler,
although this too is not really the traditional behaviour.

The first test takes about 1.5s to run, and there are likely to be
more tests in this vein once further branch types are added.  The feeling
on IRC was that 1.5s is a bit much for a single test, so I've restricted
it to SystemZ hosts for now.

The patch exposes (and fixes) some typos in the main CodeGen/SystemZ tests.
A later patch will remove the {{g}}s from that directory.

llvm-svn: 182274
2013-05-20 14:23:08 +00:00
Benjamin Kramer
216200bec5 Enable pod-like optimizations for pred and succ iterators.
llvm-svn: 182257
2013-05-20 13:12:58 +00:00
Justin Holewinski
d5636664a4 [NVPTX] Add GenericToNVVM IR converter to better handle idiomatic LLVM IR inputs
This converter currently only handles global variables in address space 0. For
these variables, they are promoted to address space 1 (global memory), and all
uses are updated to point to the result of a cvta.global instruction on the new
variable.

The motivation for this is address space 0 global variables are illegal since we
cannot declare variables in the generic address space.  Instead, we place the
variables in address space 1 and explicitly convert the pointer to address
space 0. This is primarily intended to help new users who expect to be able to
place global variables in the default address space.

llvm-svn: 182254
2013-05-20 12:13:32 +00:00
Justin Holewinski
fda22b94b1 [NVPTX] Fix i1 kernel parameters and global variables. ABI rules say we need to use .u8 for i1 parameters for kernels.
llvm-svn: 182253
2013-05-20 12:13:28 +00:00
Stepan Dyatkovskiy
adb91e7ed9 PR15868 fix.
Introduction:
In case when stack alignment is 8 and GPRs parameter part size is not N*8:
we add padding to GPRs part, so part's last byte must be recovered at
address K*8-1.
We need to do it, since remained (stack) part of parameter starts from
address K*8, and we need to "attach" "GPRs head" without gaps to it:

Stack:
|---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes...
[ [padding] [GPRs head] ] [ ------ Tail passed via stack  ------ ...

FIX:
Note, once we added padding we need to correct *all* Arg offsets that are going
after padded one. That's why we need this fix: Arg offsets were never corrected
before this patch. See new test-cases included in patch.

We also don't need to insert padding for byval parameters that are stored in GPRs
only. We need pad only last byval parameter and only in case it outsides GPRs
and stack alignment = 8.
Though, stack area, allocated for recovered byval params, must satisfy
"Size mod 8 = 0" restriction.

This patch reduces stack usage for some cases:
We can reduce ArgRegsSaveArea since inner N*4 bytes sized byval params my be
"packed" with alignment 4 in some cases.

llvm-svn: 182237
2013-05-20 08:01:34 +00:00
Renato Golin
4bb213831c Disable remote MCJIT on pre-v6 ARM
llvm-svn: 182235
2013-05-20 07:46:06 +00:00
Bob Wilson
de1f36eea4 Partially revert change in r181200 that tried to simplify JIT unit test #ifdefs.
The export list for this test requires the following symbols to be available:
  JITTest_AvailableExternallyFunction
  JITTest_AvailableExternallyGlobal
The change in r181200 commented them out, which caused the test to fail to
link, at least on Darwin. I have only reverted the change for arm, since I
can't test the other targets and since it sounds like that change was fixing
real problems for those other targets. It should be possible to rearrange the
code to keep those definitions outside the #ifdefs, but that should be done by
someone who can reproduce the problems that r181200 was trying to fix.

llvm-svn: 182233
2013-05-20 06:13:09 +00:00
Jakob Stoklund Olesen
dad0022424 Also expand 64-bit bitcasts.
llvm-svn: 182229
2013-05-20 01:01:43 +00:00
Jakob Stoklund Olesen
e033165fd4 Implement spill and fill of I64Regs.
llvm-svn: 182228
2013-05-20 00:53:25 +00:00
Jakob Stoklund Olesen
f777e6d131 Mark i64 SETCC as expand so it is turned into a SELECT_CC.
llvm-svn: 182227
2013-05-20 00:28:36 +00:00
Benjamin Kramer
1e23dfa473 Replace some bit operations with simpler ones. No functionality change.
llvm-svn: 182226
2013-05-19 22:01:57 +00:00